Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cs_cmds_cg

Group : tb.dut.u_edn_cov_if::edn_cs_cmds_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cs_cmds_cg	100.00	1	100	1	64	64

---

Group Instance : edn_cs_cmds_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance edn_cs_cmds_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	34	0	34	100.00

Variables for Group Instance edn_cs_cmds_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_acmd	5	0	5	100.00	100	1	1	0
cp_clen	2	0	2	100.00	100	1	1	0
cp_cmd_src	5	0	5	100.00	100	1	1	0
cp_flags	2	0	2	100.00	100	1	1	0
cp_glen	2	0	2	100.00	100	1	1	0
cp_mode	3	0	3	100.00	100	1	1	0

Crosses for Group Instance edn_cs_cmds_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_generate_intended	9	0	9	100.00	100	1	1	0
cr_instantiate_intended	9	0	9	100.00	100	1	1	0
cr_reseed_intended	8	0	8	100.00	100	1	1	0
cr_update_intended	2	0	2	100.00	100	1	1	0
cr_uninstantiate_intended	1	0	1	100.00	100	1	1	0
cr_acmd_mode_cmd_src_unintended	5	0	5	100.00	100	1	1	0

Summary for Variable cp_acmd

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_acmd

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[INV]	0	Excluded
auto[GENB]	0	Excluded
auto[GENU]	0	Excluded
unused	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[INS]	3186	1			T1	1		T2	1		T3	2
auto[RES]	959	1			T9	1		T5	4		T10	2
auto[GEN]	3426	1			T1	1		T2	1		T3	1
auto[UPD]	367	1			T30	1		T28	2		T68	1
auto[UNI]	2442	1			T1	1		T2	1		T3	2

---

Summary for Variable cp_clen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_clen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

some_cmd_data

3439

1

T3

3

T5

2

T10

5

no_cmd_data

6945

1

T1

3

T2

3

T3

2

---

Summary for Variable cp_cmd_src

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_cmd_src

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sw_cmd_req	8633	1			T1	3		T2	3		T3	5
reseed_cmd	573	1			T9	1		T5	4		T10	2
generate_cmd	536	1			T9	1		T5	3		T10	2
boot_gen_cmd	368	1			T25	1		T30	1		T31	1
boot_ins_cmd	274	1			T25	1		T30	1		T31	1

---

Summary for Variable cp_flags

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_flags

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

true

3618

1

T1

1

T3

4

T9

3

false

6766

1

T1

2

T2

3

T3

1

---

Summary for Variable cp_glen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_glen

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

1350

1

T5

3

T10

4

T25

1

one

2093

1

T1

1

T2

1

T3

2

---

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sw_mode	7679	1			T1	3		T2	3		T3	5
boot_mode	714	1			T25	2		T30	2		T31	2
auto_mode	1991	1			T9	6		T5	7		T10	6

---

Summary for Cross cr_generate_intended

Samples crossed: cp_acmd cp_clen cp_glen cp_mode cp_cmd_src

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	9	0	9	100.00
Automatically Generated Cross Bins	9	0	9	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_generate_intended

Excluded/Illegal bins

cp_acmd	cp_clen	cp_glen	cp_mode	cp_cmd_src	COUNT	STATUS
[auto[INV]]	[some_cmd_data , no_cmd_data]	[multiple , one]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(60 bins)
[auto[GENB] , auto[GENU]]	[some_cmd_data , no_cmd_data]	[multiple , one]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(120 bins)

Covered bins

cp_acmd

cp_clen

cp_glen

cp_mode

cp_cmd_src

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[GEN]

some_cmd_data

multiple

sw_mode

sw_cmd_req

163

1

T30

1

T66

1

T322

1

auto[GEN]

some_cmd_data

multiple

auto_mode

generate_cmd

149

1

T5

1

T10

2

T15

1

auto[GEN]

some_cmd_data

one

sw_mode

sw_cmd_req

80

1

T3

1

T14

1

T138

1

auto[GEN]

some_cmd_data

one

auto_mode

generate_cmd

119

1

T19

1

T109

1

T149

1

auto[GEN]

no_cmd_data

multiple

sw_mode

sw_cmd_req

38

1

T146

1

T152

1

T53

1

auto[GEN]

no_cmd_data

multiple

boot_mode

boot_gen_cmd

52

1

T30

1

T160

1

T82

1

auto[GEN]

no_cmd_data

multiple

auto_mode

generate_cmd

31

1

T5

1

T15

1

T48

1

auto[GEN]

no_cmd_data

one

sw_mode

sw_cmd_req

943

1

T1

1

T2

1

T4

1

auto[GEN]

no_cmd_data

one

auto_mode

generate_cmd

177

1

T9

1

T5

1

T14

1

User Defined Cross Bins for cr_generate_intended

Excluded/Illegal bins

NAME	COUNT	STATUS
not_gen	0	Excluded
gen_auto_wrong_src	0	Excluded
gen_boot_wrong_src	0	Excluded
gen_boot_seq_wrong_clen	0	Excluded
gen_boot_seq_wrong_glen	0	Excluded
gen_sw_wrong_src	0	Excluded

---

Summary for Cross cr_instantiate_intended

Samples crossed: cp_acmd cp_clen cp_flags cp_mode cp_cmd_src

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	9	0	9	100.00
Automatically Generated Cross Bins	9	0	9	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_instantiate_intended

Excluded/Illegal bins

cp_acmd	cp_clen	cp_flags	cp_mode	cp_cmd_src	COUNT	STATUS
[auto[INV]]	[some_cmd_data , no_cmd_data]	[true , false]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(60 bins)
[auto[GENB] , auto[GENU]]	[some_cmd_data , no_cmd_data]	[true , false]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(120 bins)

Covered bins

cp_acmd

cp_clen

cp_flags

cp_mode

cp_cmd_src

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[INS]

some_cmd_data

true

sw_mode

sw_cmd_req

541

1

T3

2

T6

1

T28

1

auto[INS]

some_cmd_data

true

auto_mode

sw_cmd_req

86

1

T10

1

T15

1

T42

2

auto[INS]

some_cmd_data

false

sw_mode

sw_cmd_req

605

1

T30

1

T6

3

T28

5

auto[INS]

some_cmd_data

false

auto_mode

sw_cmd_req

76

1

T14

1

T58

2

T21

1

auto[INS]

no_cmd_data

true

sw_mode

sw_cmd_req

148

1

T66

1

T69

1

T136

1

auto[INS]

no_cmd_data

true

auto_mode

sw_cmd_req

216

1

T9

1

T15

1

T19

1

auto[INS]

no_cmd_data

false

sw_mode

sw_cmd_req

1089

1

T1

1

T2

1

T4

1

auto[INS]

no_cmd_data

false

boot_mode

boot_ins_cmd

135

1

T30

1

T31

1

T77

2

auto[INS]

no_cmd_data

false

auto_mode

sw_cmd_req

151

1

T9

1

T10

1

T19

1

User Defined Cross Bins for cr_instantiate_intended

Excluded/Illegal bins

NAME	COUNT	STATUS
not_ins	0	Excluded
ins_auto_wrong_src	0	Excluded
ins_boot_wrong_src	0	Excluded
ins_boot_seq_wrong_clen	0	Excluded
ins_boot_seq_wrong_flag0	0	Excluded
ins_sw_wrong_src	0	Excluded

---

Summary for Cross cr_reseed_intended

Samples crossed: cp_acmd cp_clen cp_flags cp_mode cp_cmd_src

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	0	8	100.00
Automatically Generated Cross Bins	8	0	8	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_reseed_intended

Excluded/Illegal bins

cp_acmd	cp_clen	cp_flags	cp_mode	cp_cmd_src	COUNT	STATUS
[auto[INV]]	[some_cmd_data , no_cmd_data]	[true , false]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(60 bins)
[auto[GENB] , auto[GENU]]	[some_cmd_data , no_cmd_data]	[true , false]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(120 bins)

Covered bins

cp_acmd

cp_clen

cp_flags

cp_mode

cp_cmd_src

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[RES]

some_cmd_data

true

sw_mode

sw_cmd_req

153

1

T28

1

T69

1

T136

1

auto[RES]

some_cmd_data

true

auto_mode

reseed_cmd

137

1

T7

1

T42

1

T48

1

auto[RES]

some_cmd_data

false

sw_mode

sw_cmd_req

146

1

T68

2

T136

1

T261

1

auto[RES]

some_cmd_data

false

auto_mode

reseed_cmd

128

1

T5

1

T10

2

T14

1

auto[RES]

no_cmd_data

true

sw_mode

sw_cmd_req

34

1

T135

1

T231

2

T261

1

auto[RES]

no_cmd_data

true

auto_mode

reseed_cmd

37

1

T7

1

T42

1

T109

1

auto[RES]

no_cmd_data

false

sw_mode

sw_cmd_req

34

1

T28

1

T39

2

T41

1

auto[RES]

no_cmd_data

false

auto_mode

reseed_cmd

211

1

T9

1

T5

3

T15

2

User Defined Cross Bins for cr_reseed_intended

Excluded/Illegal bins

NAME	COUNT	STATUS
not_res	0	Excluded
res_auto_wrong_src	0	Excluded
res_boot_wrong_src	0	Excluded
res_sw_wrong_src	0	Excluded

---

Summary for Cross cr_update_intended

Samples crossed: cp_acmd cp_clen cp_mode cp_cmd_src

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	2	0	2	100.00
Automatically Generated Cross Bins	2	0	2	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_update_intended

Excluded/Illegal bins

cp_acmd	cp_clen	cp_mode	cp_cmd_src	COUNT	STATUS
[auto[INV]]	[some_cmd_data , no_cmd_data]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(30 bins)
[auto[GENB] , auto[GENU]]	[some_cmd_data , no_cmd_data]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(60 bins)

Covered bins

cp_acmd

cp_clen

cp_mode

cp_cmd_src

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UPD]

some_cmd_data

sw_mode

sw_cmd_req

280

1

T30

1

T28

2

T68

1

auto[UPD]

no_cmd_data

sw_mode

sw_cmd_req

73

1

T39

2

T132

1

T40

1

User Defined Cross Bins for cr_update_intended

Excluded/Illegal bins

NAME	COUNT	STATUS
not_upd	0	Excluded
upd_auto_wrong_src	0	Excluded
upd_boot_wrong_src	0	Excluded
upd_sw_wrong_src	0	Excluded

---

Summary for Cross cr_uninstantiate_intended

Samples crossed: cp_acmd cp_mode cp_cmd_src

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	1	0	1	100.00
Automatically Generated Cross Bins	1	0	1	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_uninstantiate_intended

Excluded/Illegal bins

cp_acmd	cp_mode	cp_cmd_src	COUNT	STATUS
[auto[INV]]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(15 bins)
[auto[GENB] , auto[GENU]]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(30 bins)

Covered bins

cp_acmd

cp_mode

cp_cmd_src

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UNI]

sw_mode

sw_cmd_req

2421

1

T1

1

T2

1

T3

2

User Defined Cross Bins for cr_uninstantiate_intended

Excluded/Illegal bins

NAME	COUNT	STATUS
not_uni	0	Excluded
uni_auto_wrong_src	0	Excluded
uni_boot_wrong_src	0	Excluded
uni_sw_wrong_src	0	Excluded

---

Summary for Cross cr_acmd_mode_cmd_src_unintended

Samples crossed: cp_acmd cp_mode cp_cmd_src

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	5	0	5	100.00
Automatically Generated Cross Bins	5	0	5	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_acmd_mode_cmd_src_unintended

Excluded/Illegal bins

cp_acmd	cp_mode	cp_cmd_src	COUNT	STATUS
[auto[INV]]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(15 bins)
[auto[GENB] , auto[GENU]]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(30 bins)

Covered bins

cp_acmd

cp_mode

cp_cmd_src

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[INS]

auto_mode

sw_cmd_req

529

1

T9

2

T10

2

T14

1

auto[RES]

auto_mode

sw_cmd_req

19

1

T152

1

T362

1

T363

1

auto[GEN]

auto_mode

sw_cmd_req

415

1

T9

2

T19

2

T32

2

auto[UPD]

auto_mode

sw_cmd_req

14

1

T151

1

T53

1

T364

1

auto[UNI]

auto_mode

sw_cmd_req

21

1

T14

1

T365

1

T12

1

User Defined Cross Bins for cr_acmd_mode_cmd_src_unintended

Excluded/Illegal bins

NAME	COUNT	STATUS
not_sw_cmd	0	Excluded
not_auto_mode	0	Excluded