Group : tb.dut.u_edn_cov_if::edn_hw_cmd_sts_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_edn_cov_if::edn_hw_cmd_sts_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
95.24 95.24 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
edn_hw_cmd_sts_cg 95.24 1 100 1 64 64



Group Instance : edn_hw_cmd_sts_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
95.24 1 100 1 64 64



Summary for Group Instance edn_hw_cmd_sts_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 16 1 15 93.75
Crosses 5 0 5 100.00


Variables for Group Instance edn_hw_cmd_sts_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_acmd 4 0 4 100.00 100 1 1 0
cp_auto_mode 2 0 2 100.00 100 1 1 0
cp_boot_mode 2 0 2 100.00 100 1 1 0
cp_cmd_ack 2 0 2 100.00 100 1 1 0
cp_cmd_sts 6 1 5 83.33 100 1 1 0


Crosses for Group Instance edn_hw_cmd_sts_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_acmd_boot_mode 3 0 3 100.00 100 1 1 0
cr_acmd_auto_mode 2 0 2 100.00 100 1 1 0


Summary for Variable cp_acmd

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_acmd

Excluded/Illegal bins
NAMECOUNTSTATUS
auto[INV] 0 Excluded
auto[UPD] 0 Excluded
auto[GENB] 0 Excluded
auto[GENU] 0 Excluded
unused 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[INS] 69 1 T32 1 T79 1 T48 1
auto[RES] 22 1 T127 1 T141 1 T328 1
auto[GEN] 91 1 T19 1 T32 1 T52 1
auto[UNI] 8 1 T48 1 T112 1 T329 1


Summary for Variable cp_auto_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_auto_mode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
not_auto_mode 326 1 T9 2 T19 1 T32 2
auto_mode 68 1 T19 1 T127 1 T52 1


Summary for Variable cp_boot_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_boot_mode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
not_boot_mode 272 1 T9 2 T19 2 T127 2
boot_mode 122 1 T32 2 T79 1 T48 2


Summary for Variable cp_cmd_ack

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_cmd_ack

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
no_ack 201 1 T9 1 T19 1 T32 1
ack 193 1 T9 1 T19 1 T32 1


Summary for Variable cp_cmd_sts

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 6 1 5 83.33


Automatically Generated Bins for cp_cmd_sts

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
auto[CMD_STS_UNDRIVEN] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[CMD_STS_SUCCESS] 205 1 T9 1 T19 1 T32 1
auto[CMD_STS_INVALID_ACMD] 45 1 T9 1 T19 1 T32 1
auto[CMD_STS_INVALID_GEN_CMD] 46 1 T114 1 T141 1 T84 1
auto[CMD_STS_INVALID_CMD_SEQ] 48 1 T149 1 T256 1 T173 1
auto[CMD_STS_RESEED_CNT_EXCEEDED] 50 1 T127 1 T48 1 T150 1


Summary for Cross cr_acmd_boot_mode

Samples crossed: cp_acmd cp_boot_mode
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 3 0 3 100.00
Automatically Generated Cross Bins 3 0 3 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_acmd_boot_mode

Excluded/Illegal bins
cp_acmdcp_boot_modeCOUNTSTATUS
[auto[INV]] [not_boot_mode , boot_mode] -- Excluded (2 bins)
[auto[UPD]] [not_boot_mode , boot_mode] -- Excluded (2 bins)
[auto[GENB] , auto[GENU]] [not_boot_mode , boot_mode] -- Excluded (4 bins)


Covered bins
cp_acmdcp_boot_modeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[INS] boot_mode 69 1 T32 1 T79 1 T48 1
auto[GEN] boot_mode 45 1 T32 1 T84 1 T157 1
auto[UNI] boot_mode 8 1 T48 1 T112 1 T329 1


User Defined Cross Bins for cr_acmd_boot_mode

Excluded/Illegal bins
NAMECOUNTSTATUS
not_boot_mode 0 Excluded
not_valid_boot_commands 0 Excluded


Summary for Cross cr_acmd_auto_mode

Samples crossed: cp_acmd cp_auto_mode
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 2 0 2 100.00
Automatically Generated Cross Bins 2 0 2 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_acmd_auto_mode

Excluded/Illegal bins
cp_acmdcp_auto_modeCOUNTSTATUS
[auto[INV]] [not_auto_mode , auto_mode] -- Excluded (2 bins)
[auto[UPD]] [not_auto_mode , auto_mode] -- Excluded (2 bins)
[auto[GENB] , auto[GENU]] [not_auto_mode , auto_mode] -- Excluded (4 bins)


Covered bins
cp_acmdcp_auto_modeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[RES] auto_mode 22 1 T127 1 T141 1 T328 1
auto[GEN] auto_mode 46 1 T19 1 T52 1 T91 1


User Defined Cross Bins for cr_acmd_auto_mode

Excluded/Illegal bins
NAMECOUNTSTATUS
not_auto_mode 0 Excluded
not_valid_boot_commands 0 Excluded

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