Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	139138	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

276063

1

T1

12

T2

5

T3

26

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	181454	1			T1	66		T2	64		T3	52
values[0x0]	110929	1			T1	7		T2	3		T3	13
values[0x1]	122818	1			T1	2		T2	4		T3	16

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	94276	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

320925

1

T1

27

T2

31

T3

42

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2012	1			T28	3		T66	1		T70	1
valid_sources[0x01]	1706	1			T3	2		T30	3		T28	3
valid_sources[0x02]	1465	1			T28	6		T15	2		T32	1
valid_sources[0x03]	1396	1			T5	1		T28	4		T69	7
valid_sources[0x04]	1491	1			T1	1		T2	3		T30	5
valid_sources[0x05]	2157	1			T28	5		T70	2		T122	1
valid_sources[0x06]	1360	1			T1	1		T6	7		T28	4
valid_sources[0x07]	1751	1			T1	1		T9	1		T30	14
valid_sources[0x08]	1944	1			T10	1		T30	2		T28	1
valid_sources[0x09]	1140	1			T9	2		T28	4		T74	1
valid_sources[0x0a]	1621	1			T28	4		T44	1		T74	1
valid_sources[0x0b]	1873	1			T3	1		T5	1		T28	5
valid_sources[0x0c]	1435	1			T5	2		T28	5		T69	3
valid_sources[0x0d]	1149	1			T28	3		T19	1		T69	1
valid_sources[0x0e]	1539	1			T28	3		T19	1		T69	3
valid_sources[0x0f]	1951	1			T28	2		T66	1		T43	6
valid_sources[0x10]	1402	1			T2	1		T5	1		T28	3
valid_sources[0x11]	1754	1			T30	2		T28	1		T66	1
valid_sources[0x12]	1267	1			T10	8		T30	5		T28	1
valid_sources[0x13]	1316	1			T28	8		T78	1		T51	1
valid_sources[0x14]	1933	1			T28	3		T19	1		T70	2
valid_sources[0x15]	1237	1			T1	1		T28	5		T15	4
valid_sources[0x16]	1626	1			T30	6		T28	2		T127	1
valid_sources[0x17]	1552	1			T10	2		T30	3		T28	3
valid_sources[0x18]	1319	1			T25	1		T28	4		T136	1
valid_sources[0x19]	2058	1			T1	1		T5	1		T28	2
valid_sources[0x1a]	1073	1			T74	1		T70	1		T127	1
valid_sources[0x1b]	1382	1			T28	3		T122	1		T69	5
valid_sources[0x1c]	1814	1			T1	1		T10	4		T28	2
valid_sources[0x1d]	1266	1			T1	1		T28	2		T32	1
valid_sources[0x1e]	1265	1			T1	2		T25	3		T30	2
valid_sources[0x1f]	1256	1			T2	1		T28	1		T69	4
valid_sources[0x20]	1315	1			T10	1		T28	5		T69	9
valid_sources[0x21]	1889	1			T9	1		T5	1		T28	1
valid_sources[0x22]	1391	1			T30	3		T28	5		T15	13
valid_sources[0x23]	1449	1			T3	2		T28	1		T122	1
valid_sources[0x24]	1166	1			T44	2		T69	3		T18	4
valid_sources[0x25]	2118	1			T2	3		T30	6		T28	6
valid_sources[0x26]	1600	1			T3	3		T28	2		T14	21
valid_sources[0x27]	2065	1			T1	1		T4	1		T5	2
valid_sources[0x28]	1382	1			T9	4		T32	2		T127	1
valid_sources[0x29]	1326	1			T2	3		T28	6		T74	1
valid_sources[0x2a]	1144	1			T9	5		T5	1		T28	3
valid_sources[0x2b]	1567	1			T4	3		T30	2		T6	2
valid_sources[0x2c]	1702	1			T5	3		T44	1		T15	1
valid_sources[0x2d]	1199	1			T5	1		T28	2		T69	1
valid_sources[0x2e]	1518	1			T28	2		T127	1		T69	8
valid_sources[0x2f]	1668	1			T28	1		T66	1		T127	1
valid_sources[0x30]	1539	1			T3	1		T5	1		T10	3
valid_sources[0x31]	1592	1			T1	1		T28	1		T66	2
valid_sources[0x32]	1669	1			T2	3		T28	2		T18	3
valid_sources[0x33]	2544	1			T30	3		T28	2		T66	1
valid_sources[0x34]	1870	1			T28	4		T144	26		T18	3
valid_sources[0x35]	2739	1			T1	1		T6	5		T28	4
valid_sources[0x36]	1435	1			T3	2		T28	3		T69	1
valid_sources[0x37]	1497	1			T1	1		T28	5		T122	1
valid_sources[0x38]	1631	1			T28	1		T70	1		T127	1
valid_sources[0x39]	1472	1			T2	1		T5	1		T28	2
valid_sources[0x3a]	1492	1			T1	1		T3	9		T9	10
valid_sources[0x3b]	2195	1			T10	5		T30	3		T28	4
valid_sources[0x3c]	1418	1			T1	1		T30	1		T6	2
valid_sources[0x3d]	1805	1			T10	1		T30	1		T28	4
valid_sources[0x3e]	2314	1			T10	2		T28	3		T7	2
valid_sources[0x3f]	1229	1			T3	3		T30	1		T6	5
valid_sources[0x40]	1775	1			T30	3		T6	1		T28	3
valid_sources[0x41]	1807	1			T2	3		T28	3		T69	2
valid_sources[0x42]	1463	1			T5	1		T28	3		T69	4
valid_sources[0x43]	1426	1			T30	2		T28	2		T15	3
valid_sources[0x44]	1488	1			T28	1		T44	1		T66	3
valid_sources[0x45]	1160	1			T30	1		T28	3		T32	3
valid_sources[0x46]	1468	1			T2	2		T28	1		T69	1
valid_sources[0x47]	1414	1			T6	1		T28	3		T19	1
valid_sources[0x48]	1642	1			T10	1		T28	1		T66	1
valid_sources[0x49]	1625	1			T4	12		T28	3		T74	2
valid_sources[0x4a]	1447	1			T28	2		T74	1		T32	1
valid_sources[0x4b]	1730	1			T30	2		T28	4		T7	9
valid_sources[0x4c]	1999	1			T2	2		T3	2		T28	3
valid_sources[0x4d]	1191	1			T28	1		T15	1		T69	3
valid_sources[0x4e]	2151	1			T10	1		T66	1		T32	1
valid_sources[0x4f]	1458	1			T5	1		T30	6		T32	1
valid_sources[0x50]	1618	1			T1	1		T5	1		T28	6
valid_sources[0x51]	1419	1			T10	10		T74	1		T32	3
valid_sources[0x52]	1815	1			T28	6		T75	10		T127	1
valid_sources[0x53]	1202	1			T1	2		T5	1		T28	3
valid_sources[0x54]	1373	1			T1	1		T28	2		T74	1
valid_sources[0x55]	1373	1			T9	4		T66	1		T69	5
valid_sources[0x56]	1602	1			T2	2		T3	1		T28	4
valid_sources[0x57]	1730	1			T28	1		T75	1		T78	1
valid_sources[0x58]	2072	1			T5	1		T30	1		T70	4
valid_sources[0x59]	1744	1			T6	9		T122	2		T69	9
valid_sources[0x5a]	1895	1			T2	3		T28	1		T69	6
valid_sources[0x5b]	1819	1			T1	1		T2	1		T9	1
valid_sources[0x5c]	1348	1			T10	2		T6	16		T28	2
valid_sources[0x5d]	1970	1			T30	1		T28	1		T70	1
valid_sources[0x5e]	1754	1			T28	4		T70	1		T122	1
valid_sources[0x5f]	1193	1			T1	1		T3	10		T28	2
valid_sources[0x60]	1752	1			T1	2		T28	5		T43	1
valid_sources[0x61]	1630	1			T1	1		T28	4		T66	1
valid_sources[0x62]	2043	1			T5	1		T28	5		T67	19
valid_sources[0x63]	1728	1			T30	3		T28	5		T70	1
valid_sources[0x64]	1446	1			T28	1		T15	3		T66	1
valid_sources[0x65]	1513	1			T30	1		T28	3		T18	2
valid_sources[0x66]	1332	1			T28	4		T121	1		T69	4
valid_sources[0x67]	1371	1			T28	1		T32	3		T45	1
valid_sources[0x68]	1618	1			T1	1		T28	3		T18	6
valid_sources[0x69]	1732	1			T9	4		T6	5		T28	3
valid_sources[0x6a]	1703	1			T1	1		T10	5		T30	2
valid_sources[0x6b]	1392	1			T1	1		T10	2		T28	2
valid_sources[0x6c]	1465	1			T1	1		T3	2		T28	3
valid_sources[0x6d]	1443	1			T1	1		T66	1		T69	1
valid_sources[0x6e]	1432	1			T7	3		T69	3		T18	1
valid_sources[0x6f]	1453	1			T30	2		T28	1		T78	1
valid_sources[0x70]	1675	1			T28	1		T31	6		T69	1
valid_sources[0x71]	1585	1			T1	1		T28	3		T7	1
valid_sources[0x72]	1695	1			T3	2		T6	3		T28	2
valid_sources[0x73]	1476	1			T1	1		T2	2		T6	4
valid_sources[0x74]	1478	1			T2	2		T30	2		T28	1
valid_sources[0x75]	1660	1			T10	5		T73	28		T6	4
valid_sources[0x76]	1599	1			T30	1		T28	1		T7	11
valid_sources[0x77]	1344	1			T1	1		T28	3		T74	1
valid_sources[0x78]	1987	1			T30	6		T28	5		T32	2
valid_sources[0x79]	1784	1			T2	2		T28	4		T14	8
valid_sources[0x7a]	1853	1			T28	2		T70	1		T122	1
valid_sources[0x7b]	1728	1			T5	1		T28	3		T44	1
valid_sources[0x7c]	1358	1			T1	1		T2	5		T30	5
valid_sources[0x7d]	1291	1			T2	4		T5	1		T28	3
valid_sources[0x7e]	1368	1			T28	5		T74	2		T69	4
valid_sources[0x7f]	1523	1			T1	1		T28	3		T19	3
valid_sources[0x80]	2080	1			T1	1		T5	1		T28	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

75343

1

T1

6

T2

2

T3

3

values[0x0]

all_enables

biggest_size

101221

1

T1

5

T2

1

T3

12

values[0x1]

all_enables

biggest_size

99499

1

T1

1

T2

2

T3

11