Group : csrng_agent_pkg::device_cmd_cg
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Group : csrng_agent_pkg::device_cmd_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
62.50 62.50 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg 62.50 1 100 1 64 64




Group Instance : csrng_agent_pkg.csrng_device_cmd_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
62.50 1 100 1 64 64




Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 52 24 28 53.85


Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
csrng_clen_cp 3 0 3 100.00 100 1 1 0
csrng_cmd_cp 5 0 5 100.00 100 1 1 0
csrng_flag_cp 2 0 2 100.00 100 1 1 0
csrng_sts 2 0 2 100.00 100 1 1 0


Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
csrng_cmd_cross 52 24 28 53.85 100 1 1 0


Summary for Variable csrng_clen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for csrng_clen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
non_zero_bins[0] 1724 1 T3 3 T10 2 T30 2
non_zero_bins[1] 1169 1 T30 1 T6 3 T28 6
zero 5690 1 T1 3 T2 3 T3 2



Summary for Variable csrng_cmd_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
il 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
upd 275 1 T30 1 T28 2 T68 1
uni 2004 1 T1 1 T2 1 T3 2
gen 2936 1 T1 1 T2 1 T3 1
res 635 1 T10 1 T28 2 T14 2
ins 2733 1 T1 1 T2 1 T3 2



Summary for Variable csrng_flag_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for csrng_flag_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
mubi_false 5487 1 T1 2 T2 3 T3 1
mubi_true 3096 1 T1 1 T3 4 T9 3



Summary for Variable csrng_sts

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for csrng_sts

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fail 36 1 T19 1 T91 1 T256 1
pass 8547 1 T1 3 T2 3 T3 5



Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 52 24 28 53.85 24
Automatically Generated Cross Bins 52 24 28 53.85 24
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for csrng_cmd_cross

Element holes
csrng_cmd_cpcsrng_clen_cpcsrng_stscsrng_flag_cpCOUNTAT LEASTNUMBERSTATUS
[upd] * [fail] * -- -- 6
[uni] [zero] [fail] * -- -- 2
[gen , res] [non_zero_bins[0] , non_zero_bins[1]] [fail] * -- -- 8
[ins] * [fail] * -- -- 6


Uncovered bins
csrng_cmd_cpcsrng_clen_cpcsrng_stscsrng_flag_cpCOUNTAT LEASTNUMBERSTATUS
[gen , res] [zero] [fail] [mubi_true] -- -- 2


Covered bins
csrng_cmd_cpcsrng_clen_cpcsrng_stscsrng_flag_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
upd non_zero_bins[0] pass mubi_false 72 1 T30 1 T28 1 T69 1
upd non_zero_bins[0] pass mubi_true 63 1 T28 1 T136 1 T318 1
upd non_zero_bins[1] pass mubi_false 45 1 T137 1 T40 2 T41 2
upd non_zero_bins[1] pass mubi_true 43 1 T68 1 T54 1 T39 1
upd zero pass mubi_false 20 1 T132 1 T41 1 T262 1
upd zero pass mubi_true 32 1 T40 1 T241 3 T319 1
uni zero pass mubi_false 1526 1 T2 1 T3 1 T30 2
uni zero pass mubi_true 478 1 T1 1 T3 1 T26 1
gen non_zero_bins[0] pass mubi_false 353 1 T6 1 T28 2 T14 1
gen non_zero_bins[0] pass mubi_true 318 1 T3 1 T30 1 T28 2
gen non_zero_bins[1] pass mubi_false 256 1 T6 1 T69 1 T136 1
gen non_zero_bins[1] pass mubi_true 224 1 T66 1 T69 2 T137 1
gen zero fail mubi_false 35 1 T19 1 T91 1 T256 1
gen zero pass mubi_false 1106 1 T1 1 T2 1 T4 1
gen zero pass mubi_true 644 1 T9 2 T25 2 T14 3
res non_zero_bins[0] pass mubi_false 144 1 T10 1 T58 1 T20 4
res non_zero_bins[0] pass mubi_true 153 1 T80 2 T138 1 T261 1
res non_zero_bins[1] pass mubi_false 96 1 T14 2 T68 2 T136 1
res non_zero_bins[1] pass mubi_true 92 1 T28 1 T42 1 T69 1
res zero fail mubi_false 1 1 T191 1 - - - -
res zero pass mubi_false 92 1 T28 1 T15 3 T127 1
res zero pass mubi_true 57 1 T135 1 T151 2 T89 3
ins non_zero_bins[0] pass mubi_false 316 1 T6 1 T28 1 T14 1
ins non_zero_bins[0] pass mubi_true 305 1 T3 2 T10 1 T6 1
ins non_zero_bins[1] pass mubi_false 221 1 T30 1 T6 2 T28 4
ins non_zero_bins[1] pass mubi_true 192 1 T28 1 T136 1 T109 1
ins zero pass mubi_false 1204 1 T1 1 T2 1 T4 1
ins zero pass mubi_true 495 1 T9 1 T25 2 T15 1


User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
uni_clen 0 Excluded

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