Group : dv_base_reg_pkg::mubi_cov#(4,32'h00000006,32'h00000009)::mubi_cg
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Group : dv_base_reg_pkg::mubi_cov#(4,32'h00000006,32'h00000009)::mubi_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_mubi_cov.sv

4 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.auto_req_mode 100.00 1 100 1 64 64
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.boot_req_mode 100.00 1 100 1 64 64
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.cmd_fifo_rst 100.00 1 100 1 64 64
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.edn_enable 100.00 1 100 1 64 64




Group Instance : mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.auto_req_mode
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.auto_req_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.auto_req_mode
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.boot_req_mode
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.boot_req_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.boot_req_mode
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.cmd_fifo_rst
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.cmd_fifo_rst

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.cmd_fifo_rst
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.edn_enable
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.edn_enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.edn_enable
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 47 1 T1 1 T9 2 T121 1
others[1] 32 1 T33 1 T359 1 T360 1
others[2] 35 1 T26 1 T63 1 T102 1
others[3] 46 1 T29 1 T32 2 T361 1
false 3450 1 T1 1 T2 1 T3 1
true 757 1 T9 1 T5 5 T10 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 29 1 T144 1 T359 1 T358 1
others[1] 26 1 T1 1 T121 1 T361 1
others[2] 31 1 T26 1 T29 1 T19 2
others[3] 63 1 T330 1 T33 3 T114 2
false 3633 1 T1 1 T2 1 T3 1
true 585 1 T25 2 T30 1 T31 2


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 18 1 T26 1 T330 1 T361 1
others[1] 26 1 T359 1 T358 3 T156 1
others[2] 29 1 T29 1 T33 1 T63 1
others[3] 36 1 T1 1 T121 1 T144 1
false 3433 1 T1 1 T2 1 T3 1
true 825 1 T4 1 T9 2 T5 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 36 1 T330 1 T359 1 T360 1
others[1] 25 1 T1 1 T26 1 T121 1
others[2] 28 1 T29 1 T127 2 T33 1
others[3] 60 1 T361 1 T63 1 T102 1
false 1928 1 T4 1 T9 5 T5 6
true 2290 1 T1 1 T2 1 T3 1

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