Unified Coverage Report :: Module :: prim_sparse_fsm_flop

Module : prim_sparse_fsm_flop

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm.u_state_regs	100.00	100.00					100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep.u_state_regs	100.00	100.00					100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep.u_state_regs	100.00	100.00					100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep.u_state_regs	100.00	100.00					100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep.u_state_regs	100.00	100.00					100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep.u_state_regs	100.00	100.00					100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep.u_state_regs	100.00	100.00					100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep.u_state_regs	100.00	100.00					100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.14	100.00	94.44		98.65	97.62	100.00	u_edn_main_sm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.14	100.00	100.00		85.71	100.00	100.00	gen_ep_blk[0].u_edn_ack_sm_ep

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.57	100.00	100.00		92.86	100.00	100.00	gen_ep_blk[1].u_edn_ack_sm_ep

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.14	100.00	100.00		85.71	100.00	100.00	gen_ep_blk[2].u_edn_ack_sm_ep

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.14	100.00	100.00		85.71	100.00	100.00	gen_ep_blk[3].u_edn_ack_sm_ep

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.57	100.00	100.00		92.86	100.00	100.00	gen_ep_blk[4].u_edn_ack_sm_ep

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.57	100.00	100.00		92.86	100.00	100.00	gen_ep_blk[5].u_edn_ack_sm_ep

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.57	100.00	100.00		92.86	100.00	100.00	gen_ep_blk[6].u_edn_ack_sm_ep

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	100.00	100.00				100.00

Line Coverage for Module : prim_sparse_fsm_flop

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
ROUTINE	47	4	4	100.00

39                        );
40         1/1            assign state_o = StateEnumT'(state_raw);
           Tests:       T1 T2 T3 
41                      
42                        `ifdef INC_ASSERT
43         1/1            assign unused_err_o = is_undefined_state(state_o);
           Tests:       T1 T2 T3 
44                      
45                        function automatic logic is_undefined_state(StateEnumT sig);
46                          // This is written with a vector in order to make it amenable to x-prop analysis.
47         1/1              logic is_defined = 1'b0;
           Tests:       T1 T2 T3 
48         1/1              for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin
           Tests:       T1 T2 T3 
49         1/1                is_defined |= (sig === t);
           Tests:       T1 T2 T3 
50                          end
51         1/1              return ~is_defined;
           Tests:       T1 T2 T3 

---

Assert Coverage for Module : prim_sparse_fsm_flop

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AssertConnected_A	7392	7392	0	0

AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7392	7392	0	0
T1	8	8	0	0
T2	8	8	0	0
T3	8	8	0	0
T4	8	8	0	0
T5	8	8	0	0
T9	8	8	0	0
T10	8	8	0	0
T25	8	8	0	0
T26	8	8	0	0
T27	8	8	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_edn_main_sm.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
ROUTINE	47	4	4	100.00

39                        );
40         1/1            assign state_o = StateEnumT'(state_raw);
           Tests:       T1 T2 T3 
41                      
42                        `ifdef INC_ASSERT
43         1/1            assign unused_err_o = is_undefined_state(state_o);
           Tests:       T1 T2 T3 
44                      
45                        function automatic logic is_undefined_state(StateEnumT sig);
46                          // This is written with a vector in order to make it amenable to x-prop analysis.
47         1/1              logic is_defined = 1'b0;
           Tests:       T1 T2 T3 
48         1/1              for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin
           Tests:       T1 T2 T3 
49         1/1                is_defined |= (sig === t);
           Tests:       T1 T2 T3 
50                          end
51         1/1              return ~is_defined;
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_edn_main_sm.u_state_regs

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AssertConnected_A	924	924	0	0

AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	924	924	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
ROUTINE	47	4	4	100.00

39                        );
40         1/1            assign state_o = StateEnumT'(state_raw);
           Tests:       T1 T2 T3 
41                      
42                        `ifdef INC_ASSERT
43         1/1            assign unused_err_o = is_undefined_state(state_o);
           Tests:       T1 T2 T3 
44                      
45                        function automatic logic is_undefined_state(StateEnumT sig);
46                          // This is written with a vector in order to make it amenable to x-prop analysis.
47         1/1              logic is_defined = 1'b0;
           Tests:       T1 T2 T3 
48         1/1              for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin
           Tests:       T1 T2 T3 
49         1/1                is_defined |= (sig === t);
           Tests:       T1 T2 T3 
50                          end
51         1/1              return ~is_defined;
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep.u_state_regs

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AssertConnected_A	924	924	0	0

AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	924	924	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
ROUTINE	47	4	4	100.00

39                        );
40         1/1            assign state_o = StateEnumT'(state_raw);
           Tests:       T1 T2 T3 
41                      
42                        `ifdef INC_ASSERT
43         1/1            assign unused_err_o = is_undefined_state(state_o);
           Tests:       T1 T2 T3 
44                      
45                        function automatic logic is_undefined_state(StateEnumT sig);
46                          // This is written with a vector in order to make it amenable to x-prop analysis.
47         1/1              logic is_defined = 1'b0;
           Tests:       T1 T2 T3 
48         1/1              for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin
           Tests:       T1 T2 T3 
49         1/1                is_defined |= (sig === t);
           Tests:       T1 T2 T3 
50                          end
51         1/1              return ~is_defined;
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep.u_state_regs

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AssertConnected_A	924	924	0	0

AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	924	924	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
ROUTINE	47	4	4	100.00

39                        );
40         1/1            assign state_o = StateEnumT'(state_raw);
           Tests:       T1 T2 T3 
41                      
42                        `ifdef INC_ASSERT
43         1/1            assign unused_err_o = is_undefined_state(state_o);
           Tests:       T1 T2 T3 
44                      
45                        function automatic logic is_undefined_state(StateEnumT sig);
46                          // This is written with a vector in order to make it amenable to x-prop analysis.
47         1/1              logic is_defined = 1'b0;
           Tests:       T1 T2 T3 
48         1/1              for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin
           Tests:       T1 T2 T3 
49         1/1                is_defined |= (sig === t);
           Tests:       T1 T2 T3 
50                          end
51         1/1              return ~is_defined;
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep.u_state_regs

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AssertConnected_A	924	924	0	0

AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	924	924	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
ROUTINE	47	4	4	100.00

39                        );
40         1/1            assign state_o = StateEnumT'(state_raw);
           Tests:       T1 T2 T3 
41                      
42                        `ifdef INC_ASSERT
43         1/1            assign unused_err_o = is_undefined_state(state_o);
           Tests:       T1 T2 T3 
44                      
45                        function automatic logic is_undefined_state(StateEnumT sig);
46                          // This is written with a vector in order to make it amenable to x-prop analysis.
47         1/1              logic is_defined = 1'b0;
           Tests:       T1 T2 T3 
48         1/1              for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin
           Tests:       T1 T2 T3 
49         1/1                is_defined |= (sig === t);
           Tests:       T1 T2 T3 
50                          end
51         1/1              return ~is_defined;
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep.u_state_regs

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AssertConnected_A	924	924	0	0

AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	924	924	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
ROUTINE	47	4	4	100.00

39                        );
40         1/1            assign state_o = StateEnumT'(state_raw);
           Tests:       T1 T2 T3 
41                      
42                        `ifdef INC_ASSERT
43         1/1            assign unused_err_o = is_undefined_state(state_o);
           Tests:       T1 T2 T3 
44                      
45                        function automatic logic is_undefined_state(StateEnumT sig);
46                          // This is written with a vector in order to make it amenable to x-prop analysis.
47         1/1              logic is_defined = 1'b0;
           Tests:       T1 T2 T3 
48         1/1              for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin
           Tests:       T1 T2 T3 
49         1/1                is_defined |= (sig === t);
           Tests:       T1 T2 T3 
50                          end
51         1/1              return ~is_defined;
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep.u_state_regs

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AssertConnected_A	924	924	0	0

AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	924	924	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
ROUTINE	47	4	4	100.00

39                        );
40         1/1            assign state_o = StateEnumT'(state_raw);
           Tests:       T1 T2 T3 
41                      
42                        `ifdef INC_ASSERT
43         1/1            assign unused_err_o = is_undefined_state(state_o);
           Tests:       T1 T2 T3 
44                      
45                        function automatic logic is_undefined_state(StateEnumT sig);
46                          // This is written with a vector in order to make it amenable to x-prop analysis.
47         1/1              logic is_defined = 1'b0;
           Tests:       T1 T2 T3 
48         1/1              for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin
           Tests:       T1 T2 T3 
49         1/1                is_defined |= (sig === t);
           Tests:       T1 T2 T3 
50                          end
51         1/1              return ~is_defined;
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep.u_state_regs

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AssertConnected_A	924	924	0	0

AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	924	924	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
ROUTINE	47	4	4	100.00

39                        );
40         1/1            assign state_o = StateEnumT'(state_raw);
           Tests:       T1 T2 T3 
41                      
42                        `ifdef INC_ASSERT
43         1/1            assign unused_err_o = is_undefined_state(state_o);
           Tests:       T1 T2 T3 
44                      
45                        function automatic logic is_undefined_state(StateEnumT sig);
46                          // This is written with a vector in order to make it amenable to x-prop analysis.
47         1/1              logic is_defined = 1'b0;
           Tests:       T1 T2 T3 
48         1/1              for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin
           Tests:       T1 T2 T3 
49         1/1                is_defined |= (sig === t);
           Tests:       T1 T2 T3 
50                          end
51         1/1              return ~is_defined;
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep.u_state_regs

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AssertConnected_A	924	924	0	0

AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	924	924	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0