Module Definition
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Module Instance : tb.dut.u_edn_core.u_prim_edge_detector_recov_alert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.31 100.00 91.03 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_edge_detector
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4511100.00
ALWAYS4833100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5311100.00

41 else begin : g_nosync 42 1/1 assign q_sync_d = d_i; Tests: T1 T2 T3  43 end : g_nosync 44 45 1/1 assign q_sync_o = q_sync_d; Tests: T1 T2 T3  46 47 always_ff @(posedge clk_i or negedge rst_ni) begin 48 2/2 if (!rst_ni) q_sync_q <= ResetValue; Tests: T1 T2 T3  | T1 T2 T3  49 1/1 else q_sync_q <= q_sync_d; Tests: T1 T2 T3  50 end 51 52 1/1 assign q_posedge_pulse_o = q_sync_d & ~q_sync_q; Tests: T1 T2 T3  53 1/1 assign q_negedge_pulse_o = ~q_sync_d & q_sync_q; Tests: T1 T2 T3 

Cond Coverage for Module : prim_edge_detector
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       52
 EXPRESSION (q_sync_d & ((~q_sync_q)))
             ----1---   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT9,T19,T32
11CoveredT9,T19,T32

 LINE       53
 EXPRESSION (((~q_sync_d)) & q_sync_q)
             ------1------   ----2---
-1--2-StatusTests
01CoveredT9,T19,T32
10CoveredT1,T2,T3
11CoveredT9,T19,T32

Branch Coverage for Module : prim_edge_detector
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 48 2 2 100.00


48 if (!rst_ni) q_sync_q <= ResetValue; -1- ==> 49 else q_sync_q <= q_sync_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%