Module Definition
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Module : prim_fifo_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd 92.86 100.00 71.43 100.00 100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd 94.64 100.00 78.57 100.00 100.00


Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.86 100.00 71.43 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.84 100.00 89.19 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.31 100.00 91.03 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.38 100.00 91.89 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.31 100.00 91.03 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_fifo_sync
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN14011100.00


68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108                           assign storage_rdata = storage[0];
109                     
110                           always_ff @(posedge clk_i)
111                             if (fifo_incr_wptr) begin
112                               storage[0] <= wdata_i;
113                             end
114                     
115                           logic unused_ptrs;
116                           assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120        1/1                assign storage_rdata = storage[fifo_rptr];
           Tests:       T1 T2 T3 
121                     
122                           always_ff @(posedge clk_i)
123        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
124        1/1                    storage[fifo_wptr] <= wdata_i;
           Tests:       T9 T5 T10 
125                             end
                        MISSING_ELSE
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T9 T5 T10 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138                           assign rdata_o = empty ? Width'(0) : rdata_int;
139                         end else begin : gen_no_output_zero
140        1/1                assign rdata_o = rdata_int;
           Tests:       T9 T5 T10 
Cond Coverage for Module : prim_fifo_sync
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT5,T10,T16
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT9,T5,T10 

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT124,T125,T126
110Not Covered
111CoveredT9,T5,T10 

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT36,T37,T38
101CoveredT9,T5,T10
110Not Covered
111CoveredT10,T14,T15
Branch Coverage for Module : prim_fifo_sync
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00 



69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



123                if (fifo_incr_wptr) begin
                   -1-     
124                  storage[fifo_wptr] <= wdata_i;
                     ==>
125                end
                   MISSING_ELSE
                   ==>

Branches:
-1-StatusTests
1 Covered T9,T5,T10
0 Covered T1,T2,T3

Assert Coverage for Module : prim_fifo_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 18789560 642343 0 0
DataKnown_AKnownEnable 19534778 19164744 0 0
DepthKnown_A 19534778 19164744 0 0
RvalidKnown_A 19534778 19164744 0 0
WreadyKnown_A 19534778 19164744 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 19117282 735461 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 18789560 642343 0 0
T5 630 300 0 0
T6 9340 0 0 0
T7 0 194 0 0
T9 4232 482 0 0
T10 4166 1688 0 0
T14 0 948 0 0
T15 0 2960 0 0
T19 0 706 0 0
T25 2024 0 0 0
T26 2698 0 0 0
T27 2220 0 0 0
T28 41860 0 0 0
T30 5634 0 0 0
T42 0 1966 0 0
T58 0 1624 0 0
T73 3464 0 0 0
T127 0 750 0 0

DataKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 19534778 19164744 0 0
T1 1880 1726 0 0
T2 3576 3388 0 0
T3 5364 5186 0 0
T4 1522 1256 0 0
T5 3930 3696 0 0
T9 4232 4066 0 0
T10 4166 3994 0 0
T25 2024 1902 0 0
T26 2698 2554 0 0
T27 2220 2116 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 19534778 19164744 0 0
T1 1880 1726 0 0
T2 3576 3388 0 0
T3 5364 5186 0 0
T4 1522 1256 0 0
T5 3930 3696 0 0
T9 4232 4066 0 0
T10 4166 3994 0 0
T25 2024 1902 0 0
T26 2698 2554 0 0
T27 2220 2116 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 19534778 19164744 0 0
T1 1880 1726 0 0
T2 3576 3388 0 0
T3 5364 5186 0 0
T4 1522 1256 0 0
T5 3930 3696 0 0
T9 4232 4066 0 0
T10 4166 3994 0 0
T25 2024 1902 0 0
T26 2698 2554 0 0
T27 2220 2116 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 19534778 19164744 0 0
T1 1880 1726 0 0
T2 3576 3388 0 0
T3 5364 5186 0 0
T4 1522 1256 0 0
T5 3930 3696 0 0
T9 4232 4066 0 0
T10 4166 3994 0 0
T25 2024 1902 0 0
T26 2698 2554 0 0
T27 2220 2116 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 19117282 735461 0 0
T5 3930 2935 0 0
T6 9340 0 0 0
T7 0 2908 0 0
T9 4232 482 0 0
T10 4166 1688 0 0
T14 0 948 0 0
T15 0 2960 0 0
T19 0 706 0 0
T25 2024 0 0 0
T26 2698 0 0 0
T27 2220 0 0 0
T28 41860 0 0 0
T30 5634 0 0 0
T42 0 1966 0 0
T73 3464 0 0 0
T77 0 294 0 0
T78 0 274 0 0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN14011100.00


68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108                           assign storage_rdata = storage[0];
109                     
110                           always_ff @(posedge clk_i)
111                             if (fifo_incr_wptr) begin
112                               storage[0] <= wdata_i;
113                             end
114                     
115                           logic unused_ptrs;
116                           assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120        1/1                assign storage_rdata = storage[fifo_rptr];
           Tests:       T1 T2 T3 
121                     
122                           always_ff @(posedge clk_i)
123        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
124        1/1                    storage[fifo_wptr] <= wdata_i;
           Tests:       T9 T5 T10 
125                             end
                        MISSING_ELSE
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T9 T5 T10 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138                           assign rdata_o = empty ? Width'(0) : rdata_int;
139                         end else begin : gen_no_output_zero
140        1/1                assign rdata_o = rdata_int;
           Tests:       T9 T5 T10 
Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
TotalCoveredPercent
Conditions141071.43
Logical141071.43
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT16,T19,T22
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT9,T5,T10 

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT9,T5,T10 

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT37,T128,T129
101CoveredT9,T5,T10
110Not Covered
111CoveredT10,T14,T15
Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00 



69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



123                if (fifo_incr_wptr) begin
                   -1-     
124                  storage[fifo_wptr] <= wdata_i;
                     ==>
125                end
                   MISSING_ELSE
                   ==>

Branches:
-1-StatusTests
1 Covered T9,T5,T10
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 9394780 314883 0 0
DataKnown_AKnownEnable 9767389 9582372 0 0
DepthKnown_A 9767389 9582372 0 0
RvalidKnown_A 9767389 9582372 0 0
WreadyKnown_A 9767389 9582372 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 9558641 361308 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9394780 314883 0 0
T5 315 85 0 0
T6 4670 0 0 0
T7 0 28 0 0
T9 2116 245 0 0
T10 2083 835 0 0
T14 0 455 0 0
T15 0 1342 0 0
T19 0 349 0 0
T25 1012 0 0 0
T26 1349 0 0 0
T27 1110 0 0 0
T28 20930 0 0 0
T30 2817 0 0 0
T42 0 967 0 0
T58 0 796 0 0
T73 1732 0 0 0
T127 0 380 0 0

DataKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 9767389 9582372 0 0
T1 940 863 0 0
T2 1788 1694 0 0
T3 2682 2593 0 0
T4 761 628 0 0
T5 1965 1848 0 0
T9 2116 2033 0 0
T10 2083 1997 0 0
T25 1012 951 0 0
T26 1349 1277 0 0
T27 1110 1058 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9767389 9582372 0 0
T1 940 863 0 0
T2 1788 1694 0 0
T3 2682 2593 0 0
T4 761 628 0 0
T5 1965 1848 0 0
T9 2116 2033 0 0
T10 2083 1997 0 0
T25 1012 951 0 0
T26 1349 1277 0 0
T27 1110 1058 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9767389 9582372 0 0
T1 940 863 0 0
T2 1788 1694 0 0
T3 2682 2593 0 0
T4 761 628 0 0
T5 1965 1848 0 0
T9 2116 2033 0 0
T10 2083 1997 0 0
T25 1012 951 0 0
T26 1349 1277 0 0
T27 1110 1058 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9767389 9582372 0 0
T1 940 863 0 0
T2 1788 1694 0 0
T3 2682 2593 0 0
T4 761 628 0 0
T5 1965 1848 0 0
T9 2116 2033 0 0
T10 2083 1997 0 0
T25 1012 951 0 0
T26 1349 1277 0 0
T27 1110 1058 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 9558641 361308 0 0
T5 1965 1361 0 0
T6 4670 0 0 0
T7 0 1377 0 0
T9 2116 245 0 0
T10 2083 835 0 0
T14 0 455 0 0
T15 0 1342 0 0
T19 0 349 0 0
T25 1012 0 0 0
T26 1349 0 0 0
T27 1110 0 0 0
T28 20930 0 0 0
T30 2817 0 0 0
T42 0 967 0 0
T73 1732 0 0 0
T77 0 148 0 0
T78 0 139 0 0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN14011100.00


68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108                           assign storage_rdata = storage[0];
109                     
110                           always_ff @(posedge clk_i)
111                             if (fifo_incr_wptr) begin
112                               storage[0] <= wdata_i;
113                             end
114                     
115                           logic unused_ptrs;
116                           assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120        1/1                assign storage_rdata = storage[fifo_rptr];
           Tests:       T1 T2 T3 
121                     
122                           always_ff @(posedge clk_i)
123        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
124        1/1                    storage[fifo_wptr] <= wdata_i;
           Tests:       T9 T5 T10 
125                             end
                        MISSING_ELSE
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T9 T5 T10 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138                           assign rdata_o = empty ? Width'(0) : rdata_int;
139                         end else begin : gen_no_output_zero
140        1/1                assign rdata_o = rdata_int;
           Tests:       T9 T5 T10 
Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT5,T10,T14
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT9,T5,T10 

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT124,T125,T126
110Not Covered
111CoveredT9,T5,T10 

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT36,T38,T130
101CoveredT9,T5,T10
110Not Covered
111CoveredT10,T14,T15
Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00 



69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



123                if (fifo_incr_wptr) begin
                   -1-     
124                  storage[fifo_wptr] <= wdata_i;
                     ==>
125                end
                   MISSING_ELSE
                   ==>

Branches:
-1-StatusTests
1 Covered T9,T5,T10
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 9394780 327460 0 0
DataKnown_AKnownEnable 9767389 9582372 0 0
DepthKnown_A 9767389 9582372 0 0
RvalidKnown_A 9767389 9582372 0 0
WreadyKnown_A 9767389 9582372 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 9558641 374153 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9394780 327460 0 0
T5 315 215 0 0
T6 4670 0 0 0
T7 0 166 0 0
T9 2116 237 0 0
T10 2083 853 0 0
T14 0 493 0 0
T15 0 1618 0 0
T19 0 357 0 0
T25 1012 0 0 0
T26 1349 0 0 0
T27 1110 0 0 0
T28 20930 0 0 0
T30 2817 0 0 0
T42 0 999 0 0
T58 0 828 0 0
T73 1732 0 0 0
T127 0 370 0 0

DataKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 9767389 9582372 0 0
T1 940 863 0 0
T2 1788 1694 0 0
T3 2682 2593 0 0
T4 761 628 0 0
T5 1965 1848 0 0
T9 2116 2033 0 0
T10 2083 1997 0 0
T25 1012 951 0 0
T26 1349 1277 0 0
T27 1110 1058 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9767389 9582372 0 0
T1 940 863 0 0
T2 1788 1694 0 0
T3 2682 2593 0 0
T4 761 628 0 0
T5 1965 1848 0 0
T9 2116 2033 0 0
T10 2083 1997 0 0
T25 1012 951 0 0
T26 1349 1277 0 0
T27 1110 1058 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9767389 9582372 0 0
T1 940 863 0 0
T2 1788 1694 0 0
T3 2682 2593 0 0
T4 761 628 0 0
T5 1965 1848 0 0
T9 2116 2033 0 0
T10 2083 1997 0 0
T25 1012 951 0 0
T26 1349 1277 0 0
T27 1110 1058 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9767389 9582372 0 0
T1 940 863 0 0
T2 1788 1694 0 0
T3 2682 2593 0 0
T4 761 628 0 0
T5 1965 1848 0 0
T9 2116 2033 0 0
T10 2083 1997 0 0
T25 1012 951 0 0
T26 1349 1277 0 0
T27 1110 1058 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 9558641 374153 0 0
T5 1965 1574 0 0
T6 4670 0 0 0
T7 0 1531 0 0
T9 2116 237 0 0
T10 2083 853 0 0
T14 0 493 0 0
T15 0 1618 0 0
T19 0 357 0 0
T25 1012 0 0 0
T26 1349 0 0 0
T27 1110 0 0 0
T28 20930 0 0 0
T30 2817 0 0 0
T42 0 999 0 0
T73 1732 0 0 0
T77 0 146 0 0
T78 0 135 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%