Module Definition
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Module Instance : tb.dut.u_edn_core.u_prim_arbiter_ppc_packer_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.16 95.00 92.31 100.00 93.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.16 95.00 92.31 100.00 93.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.31 100.00 91.03 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_arbiter_ppc
Line No.TotalCoveredPercent
TOTAL201995.00
CONT_ASSIGN5500
CONT_ASSIGN7511100.00
CONT_ASSIGN7611100.00
ALWAYS8233100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9011100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9411100.00
ALWAYS9666100.00
CONT_ASSIGN120100.00
ALWAYS12444100.00

54 logic unused_req_chk; 55 unreachable assign unused_req_chk = req_chk_i; 56 57 `ASSERT_INIT(CheckNGreaterZero_A, N > 0) 58 59 // this case is basically just a bypass 60 if (N == 1) begin : gen_degenerate_case 61 62 assign valid_o = req_i[0]; 63 assign data_o = data_i[0]; 64 assign gnt_o[0] = valid_o & ready_i; 65 assign idx_o = '0; 66 67 end else begin : gen_normal_case 68 69 logic [N-1:0] masked_req; 70 logic [N-1:0] ppc_out; 71 logic [N-1:0] arb_req; 72 logic [N-1:0] mask, mask_next; 73 logic [N-1:0] winner; 74 75 1/1 assign masked_req = mask & req_i; Tests: T1 T2 T3  76 1/1 assign arb_req = (|masked_req) ? masked_req : req_i; Tests: T1 T2 T3  77 78 // PPC 79 // Even below code looks O(n) but DC optimizes it to O(log(N)) 80 // Using Parallel Prefix Computation 81 always_comb begin 82 1/1 ppc_out[0] = arb_req[0]; Tests: T1 T2 T3  83 1/1 for (int i = 1 ; i < N ; i++) begin Tests: T1 T2 T3  84 1/1 ppc_out[i] = ppc_out[i-1] | arb_req[i]; Tests: T1 T2 T3  85 end 86 end 87 88 // Grant Generation: Leading-One detector 89 1/1 assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0}; Tests: T1 T2 T3  90 1/1 assign gnt_o = (ready_i) ? winner : '0; Tests: T1 T2 T3  91 92 1/1 assign valid_o = |req_i; Tests: T1 T2 T3  93 // Mask Generation 94 1/1 assign mask_next = {ppc_out[N-2:0], 1'b0}; Tests: T1 T2 T3  95 always_ff @(posedge clk_i or negedge rst_ni) begin 96 1/1 if (!rst_ni) begin Tests: T1 T2 T3  97 1/1 mask <= '0; Tests: T1 T2 T3  98 1/1 end else if (valid_o && ready_i) begin Tests: T1 T2 T3  99 // Latch only when requests accepted 100 1/1 mask <= mask_next; Tests: T1 T2 T3  101 1/1 end else if (valid_o && !ready_i) begin Tests: T1 T2 T3  102 // Downstream isn't yet ready so, keep current request alive. (First come first serve) 103 1/1 mask <= ppc_out; Tests: T1 T2 T3  104 end MISSING_ELSE 105 end 106 107 if (EnDataPort == 1) begin: gen_datapath 108 always_comb begin 109 data_o = '0; 110 for (int i = 0 ; i < N ; i++) begin 111 if (winner[i]) begin 112 data_o = data_i[i]; 113 end 114 end 115 end 116 end else begin: gen_nodatapath 117 assign data_o = '1; 118 // The following signal is used to avoid possible lint errors. 119 logic [DW-1:0] unused_data [N]; 120 0/1 ==> assign unused_data = data_i; 121 end 122 123 always_comb begin 124 1/1 idx_o = '0; Tests: T1 T2 T3  125 1/1 for (int unsigned i = 0 ; i < N ; i++) begin Tests: T1 T2 T3  126 1/1 if (winner[i]) begin Tests: T1 T2 T3  127 1/1 idx_o = i[IdxW-1:0]; Tests: T1 T2 T3  128 end MISSING_ELSE

Cond Coverage for Module : prim_arbiter_ppc
TotalCoveredPercent
Conditions131292.31
Logical131292.31
Non-Logical00
Event00

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT3,T9,T10
10CoveredT1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---
-1--2-StatusTests
01CoveredT4,T9,T10
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Module : prim_arbiter_ppc
Line No.TotalCoveredPercent
Branches 10 10 100.00
TERNARY 76 2 2 100.00
TERNARY 90 2 2 100.00
IF 96 4 4 100.00
IF 126 2 2 100.00


76 assign arb_req = (|masked_req) ? masked_req : req_i; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


90 assign gnt_o = (ready_i) ? winner : '0; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


96 if (!rst_ni) begin -1- 97 mask <= '0; ==> 98 end else if (valid_o && ready_i) begin -2- 99 // Latch only when requests accepted 100 mask <= mask_next; ==> 101 end else if (valid_o && !ready_i) begin -3- 102 // Downstream isn't yet ready so, keep current request alive. (First come first serve) 103 mask <= ppc_out; ==> 104 end MISSING_ELSE ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


126 if (winner[i]) begin -1- 127 idx_o = i[IdxW-1:0]; ==> 128 end MISSING_ELSE ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_arbiter_ppc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 14 93.33
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 14 93.33




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 9767389 9582372 0 0
CheckNGreaterZero_A 924 924 0 0
GntImpliesReady_A 9767389 12183 0 0
GntImpliesValid_A 9767389 12183 0 0
GrantKnown_A 9767389 9582372 0 0
IdxKnown_A 9767389 9582372 0 0
IndexIsCorrect_A 9767389 12183 0 0
LockArbDecision_A 9767389 1148656 0 0
NoReadyValidNoGrant_A 9767389 8335524 0 0
ReadyAndValidImplyGrant_A 9767389 12183 0 0
ReqAndReadyImplyGrant_A 9767389 12183 0 0
ReqImpliesValid_A 9767389 1161966 0 0
ReqStaysHighUntilGranted0_M 9767389 1148656 0 0
RoundRobin_A 9767389 0 0 924
ValidKnown_A 9767389 9582372 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9767389 9582372 0 0
T1 940 863 0 0
T2 1788 1694 0 0
T3 2682 2593 0 0
T4 761 628 0 0
T5 1965 1848 0 0
T9 2116 2033 0 0
T10 2083 1997 0 0
T25 1012 951 0 0
T26 1349 1277 0 0
T27 1110 1058 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 924 924 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9767389 12183 0 0
T1 940 1 0 0
T2 1788 1 0 0
T3 2682 1 0 0
T4 761 1 0 0
T5 1965 0 0 0
T9 2116 2 0 0
T10 2083 2 0 0
T25 1012 2 0 0
T26 1349 1 0 0
T27 1110 0 0 0
T30 0 20 0 0
T73 0 1 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9767389 12183 0 0
T1 940 1 0 0
T2 1788 1 0 0
T3 2682 1 0 0
T4 761 1 0 0
T5 1965 0 0 0
T9 2116 2 0 0
T10 2083 2 0 0
T25 1012 2 0 0
T26 1349 1 0 0
T27 1110 0 0 0
T30 0 20 0 0
T73 0 1 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9767389 9582372 0 0
T1 940 863 0 0
T2 1788 1694 0 0
T3 2682 2593 0 0
T4 761 628 0 0
T5 1965 1848 0 0
T9 2116 2033 0 0
T10 2083 1997 0 0
T25 1012 951 0 0
T26 1349 1277 0 0
T27 1110 1058 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9767389 9582372 0 0
T1 940 863 0 0
T2 1788 1694 0 0
T3 2682 2593 0 0
T4 761 628 0 0
T5 1965 1848 0 0
T9 2116 2033 0 0
T10 2083 1997 0 0
T25 1012 951 0 0
T26 1349 1277 0 0
T27 1110 1058 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9767389 12183 0 0
T1 940 1 0 0
T2 1788 1 0 0
T3 2682 1 0 0
T4 761 1 0 0
T5 1965 0 0 0
T9 2116 2 0 0
T10 2083 2 0 0
T25 1012 2 0 0
T26 1349 1 0 0
T27 1110 0 0 0
T30 0 20 0 0
T73 0 1 0 0

LockArbDecision_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9767389 1148656 0 0
T1 940 59 0 0
T2 1788 126 0 0
T3 2682 946 0 0
T4 761 0 0 0
T5 1965 1228 0 0
T9 2116 13 0 0
T10 2083 1219 0 0
T25 1012 69 0 0
T26 1349 101 0 0
T27 1110 0 0 0
T30 0 1231 0 0
T73 0 136 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9767389 8335524 0 0
T1 940 803 0 0
T2 1788 1567 0 0
T3 2682 1646 0 0
T4 761 614 0 0
T5 1965 619 0 0
T9 2116 2002 0 0
T10 2083 306 0 0
T25 1012 880 0 0
T26 1349 1175 0 0
T27 1110 1058 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9767389 12183 0 0
T1 940 1 0 0
T2 1788 1 0 0
T3 2682 1 0 0
T4 761 1 0 0
T5 1965 0 0 0
T9 2116 2 0 0
T10 2083 2 0 0
T25 1012 2 0 0
T26 1349 1 0 0
T27 1110 0 0 0
T30 0 20 0 0
T73 0 1 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9767389 12183 0 0
T1 940 1 0 0
T2 1788 1 0 0
T3 2682 1 0 0
T4 761 1 0 0
T5 1965 0 0 0
T9 2116 2 0 0
T10 2083 2 0 0
T25 1012 2 0 0
T26 1349 1 0 0
T27 1110 0 0 0
T30 0 20 0 0
T73 0 1 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9767389 1161966 0 0
T1 940 60 0 0
T2 1788 127 0 0
T3 2682 947 0 0
T4 761 1 0 0
T5 1965 1229 0 0
T9 2116 15 0 0
T10 2083 1221 0 0
T25 1012 71 0 0
T26 1349 102 0 0
T27 1110 0 0 0
T73 0 137 0 0

ReqStaysHighUntilGranted0_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9767389 1148656 0 0
T1 940 59 0 0
T2 1788 126 0 0
T3 2682 946 0 0
T4 761 0 0 0
T5 1965 1228 0 0
T9 2116 13 0 0
T10 2083 1219 0 0
T25 1012 69 0 0
T26 1349 101 0 0
T27 1110 0 0 0
T30 0 1231 0 0
T73 0 136 0 0

RoundRobin_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9767389 0 0 924

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9767389 9582372 0 0
T1 940 863 0 0
T2 1788 1694 0 0
T3 2682 2593 0 0
T4 761 628 0 0
T5 1965 1848 0 0
T9 2116 2033 0 0
T10 2083 1997 0 0
T25 1012 951 0 0
T26 1349 1277 0 0
T27 1110 1058 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%