Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	149512	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

317590

1

T1

9

T2

9

T3

32

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	198007	1			T1	26		T2	24		T3	115
values[0x0]	127013	1			T1	3		T2	5		T3	14
values[0x1]	142082	1			T1	6		T2	2		T3	16

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	100564	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

366538

1

T1

14

T2

14

T3

66

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2377	1			T70	1		T61	4		T40	1
valid_sources[0x01]	2696	1			T61	2		T74	1		T40	1
valid_sources[0x02]	2104	1			T9	2		T27	3		T61	2
valid_sources[0x03]	2567	1			T10	2		T61	3		T14	1
valid_sources[0x04]	1686	1			T29	1		T61	12		T23	1
valid_sources[0x05]	1871	1			T5	1		T10	5		T61	1
valid_sources[0x06]	2451	1			T7	4		T61	3		T62	1
valid_sources[0x07]	1492	1			T1	2		T61	6		T15	2
valid_sources[0x08]	1781	1			T20	2		T28	1		T8	4
valid_sources[0x09]	1679	1			T28	3		T61	2		T62	1
valid_sources[0x0a]	2076	1			T1	1		T2	2		T10	4
valid_sources[0x0b]	1738	1			T61	10		T23	2		T62	1
valid_sources[0x0c]	1531	1			T5	2		T10	1		T61	4
valid_sources[0x0d]	1588	1			T61	6		T23	1		T118	1
valid_sources[0x0e]	2045	1			T10	2		T61	13		T62	3
valid_sources[0x0f]	1857	1			T9	1		T10	3		T7	13
valid_sources[0x10]	1416	1			T10	2		T8	2		T61	4
valid_sources[0x11]	1969	1			T61	4		T14	1		T23	2
valid_sources[0x12]	1617	1			T7	11		T61	5		T300	3
valid_sources[0x13]	1758	1			T2	1		T30	2		T61	1
valid_sources[0x14]	1477	1			T5	1		T25	1		T61	3
valid_sources[0x15]	2150	1			T10	1		T8	1		T61	9
valid_sources[0x16]	2385	1			T10	3		T28	2		T61	2
valid_sources[0x17]	2517	1			T61	9		T74	1		T118	1
valid_sources[0x18]	1885	1			T4	19		T61	5		T62	2
valid_sources[0x19]	1877	1			T2	1		T25	1		T40	5
valid_sources[0x1a]	1545	1			T28	3		T61	4		T62	1
valid_sources[0x1b]	1561	1			T2	1		T27	1		T30	2
valid_sources[0x1c]	2188	1			T10	2		T19	1		T61	9
valid_sources[0x1d]	2125	1			T27	1		T8	3		T62	1
valid_sources[0x1e]	2004	1			T1	2		T10	1		T61	1
valid_sources[0x1f]	1529	1			T70	1		T27	3		T20	2
valid_sources[0x20]	1469	1			T61	11		T14	1		T15	2
valid_sources[0x21]	1834	1			T61	2		T62	1		T15	2
valid_sources[0x22]	1416	1			T2	1		T10	6		T61	3
valid_sources[0x23]	1574	1			T4	4		T27	1		T61	4
valid_sources[0x24]	1765	1			T61	3		T23	3		T62	1
valid_sources[0x25]	1823	1			T2	1		T27	1		T61	2
valid_sources[0x26]	2682	1			T10	3		T61	7		T62	1
valid_sources[0x27]	1850	1			T61	5		T23	7		T40	1
valid_sources[0x28]	1975	1			T10	4		T62	2		T40	2
valid_sources[0x29]	1314	1			T8	1		T14	1		T62	1
valid_sources[0x2a]	1910	1			T61	8		T31	7		T40	3
valid_sources[0x2b]	2463	1			T41	3		T40	3		T15	8
valid_sources[0x2c]	2252	1			T27	1		T61	7		T23	1
valid_sources[0x2d]	2113	1			T25	1		T8	1		T61	4
valid_sources[0x2e]	1479	1			T1	1		T27	1		T61	5
valid_sources[0x2f]	1458	1			T10	1		T61	4		T62	1
valid_sources[0x30]	1500	1			T30	2		T61	5		T62	1
valid_sources[0x31]	1248	1			T8	2		T61	3		T23	2
valid_sources[0x32]	1465	1			T19	1		T8	2		T61	15
valid_sources[0x33]	1884	1			T4	3		T61	10		T40	1
valid_sources[0x34]	2564	1			T9	40		T30	1		T20	3
valid_sources[0x35]	1651	1			T10	1		T20	3		T74	1
valid_sources[0x36]	2328	1			T2	1		T4	13		T10	1
valid_sources[0x37]	2217	1			T61	7		T40	1		T15	4
valid_sources[0x38]	1725	1			T8	1		T61	5		T53	1
valid_sources[0x39]	2315	1			T30	5		T61	1		T15	5
valid_sources[0x3a]	1548	1			T27	2		T61	1		T31	14
valid_sources[0x3b]	1768	1			T3	5		T27	1		T8	2
valid_sources[0x3c]	1951	1			T3	18		T27	2		T30	6
valid_sources[0x3d]	2118	1			T118	3		T15	3		T65	24
valid_sources[0x3e]	1771	1			T3	1		T61	6		T40	1
valid_sources[0x3f]	2129	1			T61	2		T23	2		T40	2
valid_sources[0x40]	1617	1			T70	1		T19	2		T8	1
valid_sources[0x41]	1733	1			T61	1		T15	3		T53	1
valid_sources[0x42]	1523	1			T61	5		T40	2		T15	1
valid_sources[0x43]	1546	1			T27	1		T10	1		T19	1
valid_sources[0x44]	1472	1			T5	1		T61	10		T23	4
valid_sources[0x45]	2505	1			T10	1		T61	8		T74	1
valid_sources[0x46]	1308	1			T19	1		T28	6		T61	8
valid_sources[0x47]	1486	1			T5	1		T27	2		T29	1
valid_sources[0x48]	1573	1			T10	2		T8	1		T61	5
valid_sources[0x49]	1544	1			T7	11		T61	7		T62	1
valid_sources[0x4a]	1796	1			T10	2		T8	1		T61	6
valid_sources[0x4b]	2207	1			T2	1		T61	3		T40	1
valid_sources[0x4c]	2165	1			T1	1		T30	1		T61	8
valid_sources[0x4d]	1306	1			T10	2		T20	2		T61	5
valid_sources[0x4e]	4280	1			T30	1		T61	5		T14	1
valid_sources[0x4f]	1473	1			T30	1		T61	3		T23	1
valid_sources[0x50]	1600	1			T5	1		T61	3		T23	3
valid_sources[0x51]	1627	1			T70	1		T27	1		T61	3
valid_sources[0x52]	1701	1			T1	1		T25	2		T8	2
valid_sources[0x53]	1891	1			T10	1		T20	3		T8	1
valid_sources[0x54]	1688	1			T10	1		T61	10		T31	2
valid_sources[0x55]	1455	1			T10	1		T20	3		T61	1
valid_sources[0x56]	2481	1			T1	1		T3	20		T10	4
valid_sources[0x57]	1545	1			T2	1		T61	7		T62	2
valid_sources[0x58]	1534	1			T1	2		T2	1		T16	17
valid_sources[0x59]	1700	1			T61	2		T74	1		T40	1
valid_sources[0x5a]	1546	1			T1	1		T30	1		T8	1
valid_sources[0x5b]	2084	1			T1	1		T61	6		T40	2
valid_sources[0x5c]	1585	1			T1	1		T61	5		T40	4
valid_sources[0x5d]	1857	1			T2	4		T8	1		T61	10
valid_sources[0x5e]	2182	1			T1	1		T10	1		T61	6
valid_sources[0x5f]	2062	1			T4	4		T10	3		T61	5
valid_sources[0x60]	3004	1			T3	3		T5	1		T10	2
valid_sources[0x61]	1949	1			T20	1		T62	1		T40	1
valid_sources[0x62]	1952	1			T10	5		T61	1		T74	1
valid_sources[0x63]	1707	1			T27	2		T10	4		T19	2
valid_sources[0x64]	1483	1			T20	1		T61	5		T62	1
valid_sources[0x65]	1355	1			T10	7		T30	1		T61	4
valid_sources[0x66]	1956	1			T26	1		T16	2		T9	2
valid_sources[0x67]	1432	1			T9	1		T19	1		T61	8
valid_sources[0x68]	1735	1			T20	3		T61	10		T40	1
valid_sources[0x69]	1759	1			T27	1		T61	3		T40	1
valid_sources[0x6a]	1249	1			T61	8		T40	3		T15	1
valid_sources[0x6b]	1814	1			T19	1		T40	1		T15	2
valid_sources[0x6c]	2006	1			T3	11		T19	1		T61	3
valid_sources[0x6d]	1447	1			T61	7		T62	2		T40	3
valid_sources[0x6e]	1869	1			T1	1		T10	1		T61	9
valid_sources[0x6f]	1945	1			T5	1		T27	1		T8	1
valid_sources[0x70]	1822	1			T10	5		T61	1		T62	2
valid_sources[0x71]	1951	1			T27	1		T20	3		T61	4
valid_sources[0x72]	2744	1			T61	4		T23	8		T40	1
valid_sources[0x73]	1443	1			T70	1		T7	2		T30	1
valid_sources[0x74]	1674	1			T10	1		T61	2		T31	6
valid_sources[0x75]	1746	1			T5	2		T10	4		T61	3
valid_sources[0x76]	2000	1			T1	1		T61	6		T62	1
valid_sources[0x77]	1488	1			T1	2		T19	1		T61	11
valid_sources[0x78]	1798	1			T20	3		T61	7		T40	1
valid_sources[0x79]	1539	1			T8	1		T61	2		T62	6
valid_sources[0x7a]	1574	1			T25	1		T27	1		T7	14
valid_sources[0x7b]	2257	1			T2	1		T26	1		T10	4
valid_sources[0x7c]	2001	1			T10	2		T30	1		T61	1
valid_sources[0x7d]	2035	1			T3	29		T4	3		T70	1
valid_sources[0x7e]	1690	1			T3	6		T4	6		T10	3
valid_sources[0x7f]	1556	1			T10	1		T20	2		T61	1
valid_sources[0x80]	2422	1			T70	1		T61	3		T40	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

86509

1

T1

4

T2

5

T3

6

values[0x0]

all_enables

biggest_size

116317

1

T1

2

T2

4

T3

14

values[0x1]

all_enables

biggest_size

114764

1

T1

3

T3

12

T4

25