Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	1692	1			T4	1		T10	6		T20	1
non_zero_bins[1]	1219	1			T3	2		T4	2		T20	3
zero	6143	1			T1	3		T2	3		T3	3

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	334	1			T61	1		T65	1		T115	1
uni	2187	1			T1	1		T2	1		T3	2
gen	3035	1			T1	1		T2	1		T3	1
res	582	1			T10	2		T20	3		T61	2
ins	2916	1			T1	1		T2	1		T3	2

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

5754

1

T1

3

T2

2

T3

3

mubi_true

3300

1

T2

1

T3

2

T4

3

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

40

1

T9

1

T45

1

T291

1

pass

9014

1

T1

3

T2

3

T3

5

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	74	1			T115	1		T116	1		T120	1
upd	non_zero_bins[0]	pass	mubi_true	82	1			T61	1		T112	1		T292	1
upd	non_zero_bins[1]	pass	mubi_false	61	1			T293	1		T113	1		T127	1
upd	non_zero_bins[1]	pass	mubi_true	54	1			T65	1		T112	1		T129	1
upd	zero	pass	mubi_false	33	1			T294	1		T127	1		T117	1
upd	zero	pass	mubi_true	30	1			T113	1		T56	1		T234	1
uni	zero	pass	mubi_false	1671	1			T1	1		T3	1		T4	2
uni	zero	pass	mubi_true	516	1			T2	1		T3	1		T4	1
gen	non_zero_bins[0]	pass	mubi_false	274	1			T4	1		T40	1		T115	1
gen	non_zero_bins[0]	pass	mubi_true	357	1			T10	4		T61	1		T62	1
gen	non_zero_bins[1]	pass	mubi_false	224	1			T61	2		T65	3		T115	1
gen	non_zero_bins[1]	pass	mubi_true	244	1			T61	2		T65	1		T115	2
gen	zero	fail	mubi_false	33	1			T9	1		T45	1		T291	1
gen	zero	pass	mubi_false	1206	1			T1	1		T2	1		T3	1
gen	zero	pass	mubi_true	697	1			T26	2		T9	2		T30	2
res	non_zero_bins[0]	pass	mubi_false	150	1			T10	2		T23	1		T21	4
res	non_zero_bins[0]	pass	mubi_true	103	1			T65	1		T115	1		T113	1
res	non_zero_bins[1]	pass	mubi_false	97	1			T20	3		T61	1		T40	1
res	non_zero_bins[1]	pass	mubi_true	105	1			T61	1		T65	1		T53	1
res	zero	fail	mubi_false	7	1			T174	1		T175	1		T295	1
res	zero	pass	mubi_false	73	1			T77	4		T134	1		T245	1
res	zero	pass	mubi_true	47	1			T65	1		T296	1		T297	1
ins	non_zero_bins[0]	pass	mubi_false	304	1			T61	3		T40	1		T65	1
ins	non_zero_bins[0]	pass	mubi_true	348	1			T20	1		T61	4		T23	2
ins	non_zero_bins[1]	pass	mubi_false	229	1			T3	1		T61	4		T62	1
ins	non_zero_bins[1]	pass	mubi_true	205	1			T3	1		T4	2		T65	1
ins	zero	pass	mubi_false	1318	1			T1	1		T2	1		T4	1
ins	zero	pass	mubi_true	512	1			T26	2		T16	2		T9	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded