Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=20,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 21 | 21 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
144 always_ff @(posedge clk_i or negedge rst_ni) begin
145 unreachable if (!rst_ni) begin
146 unreachable unused_logic <= MuBi4False;
147 end else begin
148 unreachable unused_logic <= mubi_i;
149 end
150 end
151
152 //VCS coverage on
153 // pragma coverage on
154
155 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T1 T2 T3
156
157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158 end
159
160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161 logic [MuBi4Width-1:0] mubi_out;
162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163 prim_buf u_prim_buf (
164 .in_i(mubi[k]),
165 .out_o(mubi_out[k])
166 );
167 end
168 20/20 assign mubi_o[j] = mubi4_t'(mubi_out);
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=4,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 5 | 5 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
144 always_ff @(posedge clk_i or negedge rst_ni) begin
145 unreachable if (!rst_ni) begin
146 unreachable unused_logic <= MuBi4False;
147 end else begin
148 unreachable unused_logic <= mubi_i;
149 end
150 end
151
152 //VCS coverage on
153 // pragma coverage on
154
155 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T1 T2 T3
156
157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158 end
159
160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161 logic [MuBi4Width-1:0] mubi_out;
162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163 prim_buf u_prim_buf (
164 .in_i(mubi[k]),
165 .out_o(mubi_out[k])
166 );
167 end
168 4/4 assign mubi_o[j] = mubi4_t'(mubi_out);
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=2,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
144 always_ff @(posedge clk_i or negedge rst_ni) begin
145 unreachable if (!rst_ni) begin
146 unreachable unused_logic <= MuBi4False;
147 end else begin
148 unreachable unused_logic <= mubi_i;
149 end
150 end
151
152 //VCS coverage on
153 // pragma coverage on
154
155 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T1 T2 T3
156
157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158 end
159
160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161 logic [MuBi4Width-1:0] mubi_out;
162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163 prim_buf u_prim_buf (
164 .in_i(mubi[k]),
165 .out_o(mubi_out[k])
166 );
167 end
168 2/2 assign mubi_o[j] = mubi4_t'(mubi_out);
Tests: T1 T2 T3 | T1 T2 T3
Assert Coverage for Module :
prim_mubi4_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3760 |
3760 |
0 |
0 |
T1 |
4 |
4 |
0 |
0 |
T2 |
4 |
4 |
0 |
0 |
T3 |
4 |
4 |
0 |
0 |
T4 |
4 |
4 |
0 |
0 |
T5 |
4 |
4 |
0 |
0 |
T6 |
4 |
4 |
0 |
0 |
T9 |
4 |
4 |
0 |
0 |
T16 |
4 |
4 |
0 |
0 |
T25 |
4 |
4 |
0 |
0 |
T26 |
4 |
4 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
47251164 |
46539980 |
0 |
0 |
T1 |
6436 |
6088 |
0 |
0 |
T2 |
4140 |
3864 |
0 |
0 |
T3 |
12024 |
11648 |
0 |
0 |
T4 |
24420 |
23592 |
0 |
0 |
T5 |
5220 |
4528 |
0 |
0 |
T6 |
9056 |
8388 |
0 |
0 |
T9 |
9032 |
8688 |
0 |
0 |
T16 |
7064 |
6432 |
0 |
0 |
T25 |
4604 |
4276 |
0 |
0 |
T26 |
4228 |
3852 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
47251164 |
46539980 |
0 |
0 |
T1 |
6436 |
6088 |
0 |
0 |
T2 |
4140 |
3864 |
0 |
0 |
T3 |
12024 |
11648 |
0 |
0 |
T4 |
24420 |
23592 |
0 |
0 |
T5 |
5220 |
4528 |
0 |
0 |
T6 |
9056 |
8388 |
0 |
0 |
T9 |
9032 |
8688 |
0 |
0 |
T16 |
7064 |
6432 |
0 |
0 |
T25 |
4604 |
4276 |
0 |
0 |
T26 |
4228 |
3852 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable
| Line No. | Total | Covered | Percent |
TOTAL | | 21 | 21 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
144 always_ff @(posedge clk_i or negedge rst_ni) begin
145 unreachable if (!rst_ni) begin
146 unreachable unused_logic <= MuBi4False;
147 end else begin
148 unreachable unused_logic <= mubi_i;
149 end
150 end
151
152 //VCS coverage on
153 // pragma coverage on
154
155 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T1 T2 T3
156
157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158 end
159
160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161 logic [MuBi4Width-1:0] mubi_out;
162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163 prim_buf u_prim_buf (
164 .in_i(mubi[k]),
165 .out_o(mubi_out[k])
166 );
167 end
168 20/20 assign mubi_o[j] = mubi4_t'(mubi_out);
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
940 |
940 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
11812791 |
11634995 |
0 |
0 |
T1 |
1609 |
1522 |
0 |
0 |
T2 |
1035 |
966 |
0 |
0 |
T3 |
3006 |
2912 |
0 |
0 |
T4 |
6105 |
5898 |
0 |
0 |
T5 |
1305 |
1132 |
0 |
0 |
T6 |
2264 |
2097 |
0 |
0 |
T9 |
2258 |
2172 |
0 |
0 |
T16 |
1766 |
1608 |
0 |
0 |
T25 |
1151 |
1069 |
0 |
0 |
T26 |
1057 |
963 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
11812791 |
11634995 |
0 |
0 |
T1 |
1609 |
1522 |
0 |
0 |
T2 |
1035 |
966 |
0 |
0 |
T3 |
3006 |
2912 |
0 |
0 |
T4 |
6105 |
5898 |
0 |
0 |
T5 |
1305 |
1132 |
0 |
0 |
T6 |
2264 |
2097 |
0 |
0 |
T9 |
2258 |
2172 |
0 |
0 |
T16 |
1766 |
1608 |
0 |
0 |
T25 |
1151 |
1069 |
0 |
0 |
T26 |
1057 |
963 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst
| Line No. | Total | Covered | Percent |
TOTAL | | 5 | 5 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
144 always_ff @(posedge clk_i or negedge rst_ni) begin
145 unreachable if (!rst_ni) begin
146 unreachable unused_logic <= MuBi4False;
147 end else begin
148 unreachable unused_logic <= mubi_i;
149 end
150 end
151
152 //VCS coverage on
153 // pragma coverage on
154
155 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T1 T2 T3
156
157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158 end
159
160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161 logic [MuBi4Width-1:0] mubi_out;
162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163 prim_buf u_prim_buf (
164 .in_i(mubi[k]),
165 .out_o(mubi_out[k])
166 );
167 end
168 4/4 assign mubi_o[j] = mubi4_t'(mubi_out);
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
940 |
940 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
11812791 |
11634995 |
0 |
0 |
T1 |
1609 |
1522 |
0 |
0 |
T2 |
1035 |
966 |
0 |
0 |
T3 |
3006 |
2912 |
0 |
0 |
T4 |
6105 |
5898 |
0 |
0 |
T5 |
1305 |
1132 |
0 |
0 |
T6 |
2264 |
2097 |
0 |
0 |
T9 |
2258 |
2172 |
0 |
0 |
T16 |
1766 |
1608 |
0 |
0 |
T25 |
1151 |
1069 |
0 |
0 |
T26 |
1057 |
963 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
11812791 |
11634995 |
0 |
0 |
T1 |
1609 |
1522 |
0 |
0 |
T2 |
1035 |
966 |
0 |
0 |
T3 |
3006 |
2912 |
0 |
0 |
T4 |
6105 |
5898 |
0 |
0 |
T5 |
1305 |
1132 |
0 |
0 |
T6 |
2264 |
2097 |
0 |
0 |
T9 |
2258 |
2172 |
0 |
0 |
T16 |
1766 |
1608 |
0 |
0 |
T25 |
1151 |
1069 |
0 |
0 |
T26 |
1057 |
963 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
144 always_ff @(posedge clk_i or negedge rst_ni) begin
145 unreachable if (!rst_ni) begin
146 unreachable unused_logic <= MuBi4False;
147 end else begin
148 unreachable unused_logic <= mubi_i;
149 end
150 end
151
152 //VCS coverage on
153 // pragma coverage on
154
155 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T1 T2 T3
156
157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158 end
159
160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161 logic [MuBi4Width-1:0] mubi_out;
162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163 prim_buf u_prim_buf (
164 .in_i(mubi[k]),
165 .out_o(mubi_out[k])
166 );
167 end
168 2/2 assign mubi_o[j] = mubi4_t'(mubi_out);
Tests: T1 T2 T3 | T1 T2 T3
Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
940 |
940 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
11812791 |
11634995 |
0 |
0 |
T1 |
1609 |
1522 |
0 |
0 |
T2 |
1035 |
966 |
0 |
0 |
T3 |
3006 |
2912 |
0 |
0 |
T4 |
6105 |
5898 |
0 |
0 |
T5 |
1305 |
1132 |
0 |
0 |
T6 |
2264 |
2097 |
0 |
0 |
T9 |
2258 |
2172 |
0 |
0 |
T16 |
1766 |
1608 |
0 |
0 |
T25 |
1151 |
1069 |
0 |
0 |
T26 |
1057 |
963 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
11812791 |
11634995 |
0 |
0 |
T1 |
1609 |
1522 |
0 |
0 |
T2 |
1035 |
966 |
0 |
0 |
T3 |
3006 |
2912 |
0 |
0 |
T4 |
6105 |
5898 |
0 |
0 |
T5 |
1305 |
1132 |
0 |
0 |
T6 |
2264 |
2097 |
0 |
0 |
T9 |
2258 |
2172 |
0 |
0 |
T16 |
1766 |
1608 |
0 |
0 |
T25 |
1151 |
1069 |
0 |
0 |
T26 |
1057 |
963 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
144 always_ff @(posedge clk_i or negedge rst_ni) begin
145 unreachable if (!rst_ni) begin
146 unreachable unused_logic <= MuBi4False;
147 end else begin
148 unreachable unused_logic <= mubi_i;
149 end
150 end
151
152 //VCS coverage on
153 // pragma coverage on
154
155 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T1 T2 T3
156
157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158 end
159
160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161 logic [MuBi4Width-1:0] mubi_out;
162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163 prim_buf u_prim_buf (
164 .in_i(mubi[k]),
165 .out_o(mubi_out[k])
166 );
167 end
168 2/2 assign mubi_o[j] = mubi4_t'(mubi_out);
Tests: T1 T2 T3 | T1 T2 T3
Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
940 |
940 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
11812791 |
11634995 |
0 |
0 |
T1 |
1609 |
1522 |
0 |
0 |
T2 |
1035 |
966 |
0 |
0 |
T3 |
3006 |
2912 |
0 |
0 |
T4 |
6105 |
5898 |
0 |
0 |
T5 |
1305 |
1132 |
0 |
0 |
T6 |
2264 |
2097 |
0 |
0 |
T9 |
2258 |
2172 |
0 |
0 |
T16 |
1766 |
1608 |
0 |
0 |
T25 |
1151 |
1069 |
0 |
0 |
T26 |
1057 |
963 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
11812791 |
11634995 |
0 |
0 |
T1 |
1609 |
1522 |
0 |
0 |
T2 |
1035 |
966 |
0 |
0 |
T3 |
3006 |
2912 |
0 |
0 |
T4 |
6105 |
5898 |
0 |
0 |
T5 |
1305 |
1132 |
0 |
0 |
T6 |
2264 |
2097 |
0 |
0 |
T9 |
2258 |
2172 |
0 |
0 |
T16 |
1766 |
1608 |
0 |
0 |
T25 |
1151 |
1069 |
0 |
0 |
T26 |
1057 |
963 |
0 |
0 |