Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	160488	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

325563

1

T1

8

T2

8

T3

34

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	210053	1			T1	23		T2	46		T3	55
values[0x0]	130256	1			T1	2		T2	2		T3	13
values[0x1]	145742	1			T1	7		T2	7		T3	21

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	107872	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

378179

1

T1

13

T2

21

T3

49

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2211	1			T1	1		T42	16		T12	1
valid_sources[0x01]	1691	1			T83	4		T17	3		T16	1
valid_sources[0x02]	1747	1			T42	18		T17	2		T18	1
valid_sources[0x03]	1802	1			T56	20		T17	3		T18	7
valid_sources[0x04]	1543	1			T27	2		T37	1		T28	1
valid_sources[0x05]	1821	1			T10	1		T12	1		T56	2
valid_sources[0x06]	2259	1			T29	1		T67	1		T12	1
valid_sources[0x07]	2008	1			T42	2		T70	9		T56	5
valid_sources[0x08]	1513	1			T10	1		T28	1		T17	3
valid_sources[0x09]	1809	1			T10	4		T83	2		T17	5
valid_sources[0x0a]	2967	1			T3	1		T10	3		T29	2
valid_sources[0x0b]	2688	1			T31	1		T56	7		T17	9
valid_sources[0x0c]	1457	1			T31	1		T42	1		T83	2
valid_sources[0x0d]	1740	1			T10	4		T17	1		T18	10
valid_sources[0x0e]	1901	1			T27	2		T56	2		T17	5
valid_sources[0x0f]	1574	1			T1	1		T42	24		T17	6
valid_sources[0x10]	1839	1			T5	2		T10	1		T29	1
valid_sources[0x11]	2021	1			T17	1		T62	1		T114	2
valid_sources[0x12]	2780	1			T3	4		T29	1		T31	1
valid_sources[0x13]	1700	1			T26	1		T67	1		T42	4
valid_sources[0x14]	2483	1			T25	2		T17	6		T30	5
valid_sources[0x15]	1509	1			T3	1		T42	1		T56	4
valid_sources[0x16]	1815	1			T29	1		T17	4		T18	1
valid_sources[0x17]	1787	1			T29	1		T11	5		T42	22
valid_sources[0x18]	1925	1			T24	1		T25	1		T56	9
valid_sources[0x19]	1818	1			T42	2		T65	1		T17	3
valid_sources[0x1a]	1898	1			T5	1		T10	1		T27	1
valid_sources[0x1b]	1487	1			T27	2		T37	2		T11	3
valid_sources[0x1c]	1601	1			T17	4		T18	5		T114	2
valid_sources[0x1d]	1950	1			T68	2		T12	1		T17	7
valid_sources[0x1e]	1785	1			T3	2		T56	5		T17	2
valid_sources[0x1f]	1771	1			T67	1		T56	16		T17	5
valid_sources[0x20]	1821	1			T10	1		T65	1		T56	2
valid_sources[0x21]	1583	1			T42	3		T56	16		T17	7
valid_sources[0x22]	1613	1			T3	1		T56	6		T83	3
valid_sources[0x23]	1961	1			T29	1		T17	3		T16	1
valid_sources[0x24]	1957	1			T3	1		T31	1		T56	3
valid_sources[0x25]	1795	1			T31	2		T30	3		T45	1
valid_sources[0x26]	2063	1			T29	1		T19	2		T31	1
valid_sources[0x27]	2003	1			T56	5		T17	2		T16	1
valid_sources[0x28]	1716	1			T31	1		T56	4		T17	2
valid_sources[0x29]	2343	1			T29	1		T31	1		T42	1
valid_sources[0x2a]	1770	1			T37	1		T42	2		T56	8
valid_sources[0x2b]	3070	1			T10	1		T29	1		T68	1
valid_sources[0x2c]	1600	1			T56	1		T17	1		T16	1
valid_sources[0x2d]	1614	1			T17	2		T49	15		T114	5
valid_sources[0x2e]	1571	1			T29	1		T11	8		T67	1
valid_sources[0x2f]	2023	1			T17	10		T16	1		T114	6
valid_sources[0x30]	1754	1			T10	2		T56	1		T17	1
valid_sources[0x31]	1726	1			T42	4		T56	5		T17	2
valid_sources[0x32]	1571	1			T10	1		T17	3		T114	1
valid_sources[0x33]	1766	1			T29	2		T17	2		T62	1
valid_sources[0x34]	2029	1			T17	3		T16	2		T18	5
valid_sources[0x35]	1436	1			T17	1		T30	3		T114	2
valid_sources[0x36]	2391	1			T37	1		T29	3		T17	4
valid_sources[0x37]	1477	1			T5	2		T68	1		T42	1
valid_sources[0x38]	1667	1			T19	2		T67	1		T12	1
valid_sources[0x39]	1620	1			T68	1		T56	2		T17	1
valid_sources[0x3a]	1836	1			T27	3		T29	1		T12	1
valid_sources[0x3b]	3468	1			T26	5		T31	1		T56	4
valid_sources[0x3c]	2146	1			T3	2		T25	43		T29	2
valid_sources[0x3d]	2356	1			T10	4		T29	1		T42	5
valid_sources[0x3e]	2215	1			T3	1		T27	1		T17	3
valid_sources[0x3f]	2483	1			T29	1		T67	2		T56	3
valid_sources[0x40]	2500	1			T29	1		T11	1		T17	6
valid_sources[0x41]	2015	1			T29	1		T42	2		T56	22
valid_sources[0x42]	1411	1			T31	1		T42	7		T12	1
valid_sources[0x43]	1699	1			T2	55		T3	2		T31	1
valid_sources[0x44]	1945	1			T3	1		T19	3		T56	5
valid_sources[0x45]	1863	1			T31	1		T56	10		T83	1
valid_sources[0x46]	1813	1			T10	2		T67	1		T56	1
valid_sources[0x47]	1816	1			T24	2		T27	3		T56	3
valid_sources[0x48]	1751	1			T26	2		T67	1		T17	7
valid_sources[0x49]	1737	1			T3	1		T33	1		T114	2
valid_sources[0x4a]	2473	1			T12	8		T83	1		T17	4
valid_sources[0x4b]	2013	1			T10	1		T37	4		T42	4
valid_sources[0x4c]	1818	1			T3	1		T10	1		T29	1
valid_sources[0x4d]	2035	1			T3	1		T37	1		T31	1
valid_sources[0x4e]	1842	1			T10	1		T29	1		T68	1
valid_sources[0x4f]	2004	1			T10	1		T19	1		T68	2
valid_sources[0x50]	1912	1			T12	1		T17	1		T126	1
valid_sources[0x51]	1593	1			T10	2		T19	4		T70	1
valid_sources[0x52]	1555	1			T29	1		T11	10		T68	4
valid_sources[0x53]	1643	1			T37	1		T42	3		T12	2
valid_sources[0x54]	1810	1			T25	1		T29	1		T42	1
valid_sources[0x55]	1736	1			T27	1		T19	1		T56	6
valid_sources[0x56]	1834	1			T3	1		T10	1		T17	2
valid_sources[0x57]	1650	1			T10	2		T29	1		T17	5
valid_sources[0x58]	1556	1			T27	1		T42	5		T56	1
valid_sources[0x59]	2203	1			T42	4		T17	2		T16	2
valid_sources[0x5a]	2123	1			T28	1		T12	1		T17	9
valid_sources[0x5b]	1938	1			T42	5		T18	2		T45	4
valid_sources[0x5c]	1630	1			T67	1		T42	2		T17	1
valid_sources[0x5d]	1890	1			T10	3		T68	1		T42	8
valid_sources[0x5e]	1666	1			T31	1		T17	2		T114	2
valid_sources[0x5f]	1452	1			T27	3		T11	3		T17	6
valid_sources[0x60]	1459	1			T29	1		T12	2		T17	3
valid_sources[0x61]	1430	1			T17	5		T16	1		T18	3
valid_sources[0x62]	1838	1			T56	2		T17	4		T16	2
valid_sources[0x63]	2334	1			T3	2		T24	1		T17	2
valid_sources[0x64]	1625	1			T3	2		T70	2		T17	8
valid_sources[0x65]	1814	1			T27	1		T11	3		T42	3
valid_sources[0x66]	1715	1			T10	2		T27	4		T17	5
valid_sources[0x67]	2393	1			T3	2		T5	1		T29	1
valid_sources[0x68]	2258	1			T42	4		T83	1		T17	8
valid_sources[0x69]	1761	1			T31	1		T11	4		T67	1
valid_sources[0x6a]	1889	1			T3	4		T25	1		T12	1
valid_sources[0x6b]	1668	1			T3	1		T10	1		T31	2
valid_sources[0x6c]	1512	1			T10	1		T37	1		T17	2
valid_sources[0x6d]	1709	1			T32	14		T17	1		T16	1
valid_sources[0x6e]	1667	1			T25	1		T31	1		T42	3
valid_sources[0x6f]	1529	1			T27	1		T56	15		T17	1
valid_sources[0x70]	1821	1			T3	2		T25	1		T42	10
valid_sources[0x71]	1806	1			T3	3		T17	3		T16	2
valid_sources[0x72]	1617	1			T3	2		T17	4		T114	9
valid_sources[0x73]	2392	1			T17	2		T114	3		T270	3
valid_sources[0x74]	2721	1			T3	3		T10	1		T19	2
valid_sources[0x75]	1795	1			T3	1		T29	1		T67	1
valid_sources[0x76]	2681	1			T42	5		T56	3		T17	1
valid_sources[0x77]	1773	1			T5	1		T10	1		T31	1
valid_sources[0x78]	1422	1			T1	3		T3	1		T11	6
valid_sources[0x79]	1837	1			T29	2		T56	3		T17	2
valid_sources[0x7a]	1676	1			T27	1		T67	1		T56	14
valid_sources[0x7b]	2032	1			T31	1		T42	4		T65	1
valid_sources[0x7c]	2390	1			T3	1		T6	918		T56	12
valid_sources[0x7d]	1573	1			T10	4		T27	2		T17	6
valid_sources[0x7e]	1666	1			T10	1		T56	4		T17	4
valid_sources[0x7f]	1867	1			T10	1		T56	11		T17	5
valid_sources[0x80]	2154	1			T3	4		T56	3		T17	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

88918

1

T1

4

T2

3

T3

3

values[0x0]

all_enables

biggest_size

119211

1

T2

1

T3

12

T4

3

values[0x1]

all_enables

biggest_size

117434

1

T1

4

T2

4

T3

19