Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	1776	1			T3	1		T10	2		T6	7
non_zero_bins[1]	1375	1			T3	2		T10	3		T6	10
zero	6413	1			T1	3		T2	3		T3	1

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	315	1			T6	4		T29	1		T42	1
uni	2323	1			T1	1		T2	1		T3	1
gen	3228	1			T1	1		T2	1		T3	1
res	650	1			T3	1		T10	3		T6	2
ins	3048	1			T1	1		T2	1		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

6006

1

T1

2

T2

2

T3

2

mubi_true

3558

1

T1

1

T2

1

T3

2

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

33

1

T52

1

T55

1

T100

1

pass

9531

1

T1

3

T2

3

T3

4

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	83	1			T117	1		T118	1		T38	2
upd	non_zero_bins[0]	pass	mubi_true	67	1			T132	1		T48	1		T313	1
upd	non_zero_bins[1]	pass	mubi_false	60	1			T6	1		T114	1		T110	1
upd	non_zero_bins[1]	pass	mubi_true	42	1			T6	1		T42	1		T114	1
upd	zero	pass	mubi_false	29	1			T6	1		T56	1		T116	1
upd	zero	pass	mubi_true	34	1			T6	1		T29	1		T50	1
uni	zero	pass	mubi_false	1760	1			T3	1		T37	1		T6	10
uni	zero	pass	mubi_true	563	1			T1	1		T2	1		T27	1
gen	non_zero_bins[0]	pass	mubi_false	292	1			T6	1		T29	1		T11	4
gen	non_zero_bins[0]	pass	mubi_true	351	1			T6	1		T41	1		T114	1
gen	non_zero_bins[1]	pass	mubi_false	238	1			T3	1		T56	1		T114	1
gen	non_zero_bins[1]	pass	mubi_true	344	1			T6	3		T42	1		T114	1
gen	zero	fail	mubi_false	29	1			T52	1		T55	1		T100	1
gen	zero	pass	mubi_false	1244	1			T1	1		T2	1		T4	1
gen	zero	pass	mubi_true	730	1			T5	1		T24	1		T10	3
res	non_zero_bins[0]	pass	mubi_false	146	1			T6	2		T11	2		T56	1
res	non_zero_bins[0]	pass	mubi_true	148	1			T111	1		T78	2		T117	2
res	non_zero_bins[1]	pass	mubi_false	105	1			T114	1		T21	2		T110	1
res	non_zero_bins[1]	pass	mubi_true	93	1			T3	1		T10	3		T42	1
res	zero	fail	mubi_false	4	1			T173	1		T175	1		T314	1
res	zero	pass	mubi_false	70	1			T11	2		T16	3		T78	2
res	zero	pass	mubi_true	84	1			T62	2		T265	1		T171	4
ins	non_zero_bins[0]	pass	mubi_false	341	1			T10	1		T6	1		T11	1
ins	non_zero_bins[0]	pass	mubi_true	348	1			T3	1		T10	1		T6	2
ins	non_zero_bins[1]	pass	mubi_false	263	1			T6	3		T56	1		T16	1
ins	non_zero_bins[1]	pass	mubi_true	230	1			T6	2		T56	2		T114	2
ins	zero	pass	mubi_false	1342	1			T1	1		T2	1		T4	1
ins	zero	pass	mubi_true	524	1			T25	1		T6	2		T28	2

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded