Module Definition
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Module : prim_fifo_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/edn-sim-vcs/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd 94.64 100.00 78.57 100.00 100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd 94.64 100.00 78.57 100.00 100.00


Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.38 100.00 91.89 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.31 100.00 91.03 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.38 100.00 91.89 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.31 100.00 91.03 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_fifo_sync
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN14011100.00


68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108                           assign storage_rdata = storage[0];
109                     
110                           always_ff @(posedge clk_i)
111                             if (fifo_incr_wptr) begin
112                               storage[0] <= wdata_i;
113                             end
114                     
115                           logic unused_ptrs;
116                           assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120        1/1                assign storage_rdata = storage[fifo_rptr];
           Tests:       T1 T2 T3 
121                     
122                           always_ff @(posedge clk_i)
123        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
124        1/1                    storage[fifo_wptr] <= wdata_i;
           Tests:       T5 T10 T19 
125                             end
                        MISSING_ELSE
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T5 T10 T19 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138                           assign rdata_o = empty ? Width'(0) : rdata_int;
139                         end else begin : gen_no_output_zero
140        1/1                assign rdata_o = rdata_int;
           Tests:       T5 T10 T19 
Cond Coverage for Module : prim_fifo_sync
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT10,T19,T11
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT5,T10,T19 

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT33,T104,T105
110Not Covered
111CoveredT5,T10,T19 

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT30,T35,T36
101CoveredT5,T10,T19
110Not Covered
111CoveredT10,T11,T16
Branch Coverage for Module : prim_fifo_sync
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00 



69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



123                if (fifo_incr_wptr) begin
                   -1-     
124                  storage[fifo_wptr] <= wdata_i;
                     ==>
125                end
                   MISSING_ELSE
                   ==>

Branches:
-1-StatusTests
1 Covered T5,T10,T19
0 Covered T1,T2,T3

Assert Coverage for Module : prim_fifo_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 22969270 1008944 0 0
DataKnown_AKnownEnable 23762372 23363718 0 0
DepthKnown_A 23762372 23363718 0 0
RvalidKnown_A 23762372 23363718 0 0
WreadyKnown_A 23762372 23363718 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 23339230 1108111 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 22969270 1008944 0 0
T6 53412 0 0 0
T10 5494 2815 0 0
T11 0 4387 0 0
T12 0 301 0 0
T16 0 6290 0 0
T19 3902 73 0 0
T21 0 2742 0 0
T23 0 3225 0 0
T25 4078 0 0 0
T26 2356 0 0 0
T27 2764 0 0 0
T28 1618 0 0 0
T29 3078 0 0 0
T32 140 0 0 0
T37 2532 0 0 0
T45 0 2192 0 0
T52 0 492 0 0
T62 0 2399 0 0

DataKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 23762372 23363718 0 0
T1 2958 2774 0 0
T2 1808 1636 0 0
T3 7670 7482 0 0
T4 1778 1540 0 0
T5 3566 3208 0 0
T10 5494 5316 0 0
T24 1764 1658 0 0
T25 4078 3924 0 0
T26 2356 2182 0 0
T27 2764 2590 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 23762372 23363718 0 0
T1 2958 2774 0 0
T2 1808 1636 0 0
T3 7670 7482 0 0
T4 1778 1540 0 0
T5 3566 3208 0 0
T10 5494 5316 0 0
T24 1764 1658 0 0
T25 4078 3924 0 0
T26 2356 2182 0 0
T27 2764 2590 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 23762372 23363718 0 0
T1 2958 2774 0 0
T2 1808 1636 0 0
T3 7670 7482 0 0
T4 1778 1540 0 0
T5 3566 3208 0 0
T10 5494 5316 0 0
T24 1764 1658 0 0
T25 4078 3924 0 0
T26 2356 2182 0 0
T27 2764 2590 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 23762372 23363718 0 0
T1 2958 2774 0 0
T2 1808 1636 0 0
T3 7670 7482 0 0
T4 1778 1540 0 0
T5 3566 3208 0 0
T10 5494 5316 0 0
T24 1764 1658 0 0
T25 4078 3924 0 0
T26 2356 2182 0 0
T27 2764 2590 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 23339230 1108111 0 0
T5 3566 220 0 0
T6 53412 0 0 0
T10 5494 2815 0 0
T11 0 4387 0 0
T12 0 301 0 0
T16 0 6290 0 0
T19 0 73 0 0
T24 1764 0 0 0
T25 4078 0 0 0
T26 2356 0 0 0
T27 2764 0 0 0
T28 1618 0 0 0
T29 3078 0 0 0
T31 0 7 0 0
T32 0 238 0 0
T37 2532 0 0 0
T52 0 248 0 0
T62 0 2399 0 0
T70 0 274 0 0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN14011100.00


68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108                           assign storage_rdata = storage[0];
109                     
110                           always_ff @(posedge clk_i)
111                             if (fifo_incr_wptr) begin
112                               storage[0] <= wdata_i;
113                             end
114                     
115                           logic unused_ptrs;
116                           assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120        1/1                assign storage_rdata = storage[fifo_rptr];
           Tests:       T1 T2 T3 
121                     
122                           always_ff @(posedge clk_i)
123        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
124        1/1                    storage[fifo_wptr] <= wdata_i;
           Tests:       T5 T10 T19 
125                             end
                        MISSING_ELSE
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T5 T10 T19 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138                           assign rdata_o = empty ? Width'(0) : rdata_int;
139                         end else begin : gen_no_output_zero
140        1/1                assign rdata_o = rdata_int;
           Tests:       T5 T10 T19 
Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT10,T17,T21
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT5,T10,T19 

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT105,T106
110Not Covered
111CoveredT5,T10,T19 

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT30,T35,T107
101CoveredT5,T10,T19
110Not Covered
111CoveredT10,T11,T16
Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00 



69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



123                if (fifo_incr_wptr) begin
                   -1-     
124                  storage[fifo_wptr] <= wdata_i;
                     ==>
125                end
                   MISSING_ELSE
                   ==>

Branches:
-1-StatusTests
1 Covered T5,T10,T19
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 11484635 498920 0 0
DataKnown_AKnownEnable 11881186 11681859 0 0
DepthKnown_A 11881186 11681859 0 0
RvalidKnown_A 11881186 11681859 0 0
WreadyKnown_A 11881186 11681859 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 11669615 548264 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11484635 498920 0 0
T6 26706 0 0 0
T10 2747 1406 0 0
T11 0 2172 0 0
T12 0 153 0 0
T16 0 3045 0 0
T19 1951 25 0 0
T21 0 1380 0 0
T23 0 1605 0 0
T25 2039 0 0 0
T26 1178 0 0 0
T27 1382 0 0 0
T28 809 0 0 0
T29 1539 0 0 0
T32 70 0 0 0
T37 1266 0 0 0
T45 0 1038 0 0
T52 0 248 0 0
T62 0 1167 0 0

DataKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 11881186 11681859 0 0
T1 1479 1387 0 0
T2 904 818 0 0
T3 3835 3741 0 0
T4 889 770 0 0
T5 1783 1604 0 0
T10 2747 2658 0 0
T24 882 829 0 0
T25 2039 1962 0 0
T26 1178 1091 0 0
T27 1382 1295 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11881186 11681859 0 0
T1 1479 1387 0 0
T2 904 818 0 0
T3 3835 3741 0 0
T4 889 770 0 0
T5 1783 1604 0 0
T10 2747 2658 0 0
T24 882 829 0 0
T25 2039 1962 0 0
T26 1178 1091 0 0
T27 1382 1295 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11881186 11681859 0 0
T1 1479 1387 0 0
T2 904 818 0 0
T3 3835 3741 0 0
T4 889 770 0 0
T5 1783 1604 0 0
T10 2747 2658 0 0
T24 882 829 0 0
T25 2039 1962 0 0
T26 1178 1091 0 0
T27 1382 1295 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11881186 11681859 0 0
T1 1479 1387 0 0
T2 904 818 0 0
T3 3835 3741 0 0
T4 889 770 0 0
T5 1783 1604 0 0
T10 2747 2658 0 0
T24 882 829 0 0
T25 2039 1962 0 0
T26 1178 1091 0 0
T27 1382 1295 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 11669615 548264 0 0
T5 1783 111 0 0
T6 26706 0 0 0
T10 2747 1406 0 0
T11 0 2172 0 0
T12 0 153 0 0
T16 0 3045 0 0
T19 0 25 0 0
T24 882 0 0 0
T25 2039 0 0 0
T26 1178 0 0 0
T27 1382 0 0 0
T28 809 0 0 0
T29 1539 0 0 0
T32 0 120 0 0
T37 1266 0 0 0
T52 0 248 0 0
T62 0 1167 0 0
T70 0 142 0 0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN14011100.00


68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108                           assign storage_rdata = storage[0];
109                     
110                           always_ff @(posedge clk_i)
111                             if (fifo_incr_wptr) begin
112                               storage[0] <= wdata_i;
113                             end
114                     
115                           logic unused_ptrs;
116                           assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120        1/1                assign storage_rdata = storage[fifo_rptr];
           Tests:       T1 T2 T3 
121                     
122                           always_ff @(posedge clk_i)
123        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
124        1/1                    storage[fifo_wptr] <= wdata_i;
           Tests:       T5 T10 T19 
125                             end
                        MISSING_ELSE
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T5 T10 T19 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138                           assign rdata_o = empty ? Width'(0) : rdata_int;
139                         end else begin : gen_no_output_zero
140        1/1                assign rdata_o = rdata_int;
           Tests:       T5 T10 T19 
Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT10,T19,T11
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT5,T10,T19 

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT33,T104,T108
110Not Covered
111CoveredT5,T10,T19 

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT36
101CoveredT5,T10,T19
110Not Covered
111CoveredT10,T11,T16
Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00 



69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



123                if (fifo_incr_wptr) begin
                   -1-     
124                  storage[fifo_wptr] <= wdata_i;
                     ==>
125                end
                   MISSING_ELSE
                   ==>

Branches:
-1-StatusTests
1 Covered T5,T10,T19
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 11484635 510024 0 0
DataKnown_AKnownEnable 11881186 11681859 0 0
DepthKnown_A 11881186 11681859 0 0
RvalidKnown_A 11881186 11681859 0 0
WreadyKnown_A 11881186 11681859 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 11669615 559847 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11484635 510024 0 0
T6 26706 0 0 0
T10 2747 1409 0 0
T11 0 2215 0 0
T12 0 148 0 0
T16 0 3245 0 0
T19 1951 48 0 0
T21 0 1362 0 0
T23 0 1620 0 0
T25 2039 0 0 0
T26 1178 0 0 0
T27 1382 0 0 0
T28 809 0 0 0
T29 1539 0 0 0
T32 70 0 0 0
T37 1266 0 0 0
T45 0 1154 0 0
T52 0 244 0 0
T62 0 1232 0 0

DataKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 11881186 11681859 0 0
T1 1479 1387 0 0
T2 904 818 0 0
T3 3835 3741 0 0
T4 889 770 0 0
T5 1783 1604 0 0
T10 2747 2658 0 0
T24 882 829 0 0
T25 2039 1962 0 0
T26 1178 1091 0 0
T27 1382 1295 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11881186 11681859 0 0
T1 1479 1387 0 0
T2 904 818 0 0
T3 3835 3741 0 0
T4 889 770 0 0
T5 1783 1604 0 0
T10 2747 2658 0 0
T24 882 829 0 0
T25 2039 1962 0 0
T26 1178 1091 0 0
T27 1382 1295 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11881186 11681859 0 0
T1 1479 1387 0 0
T2 904 818 0 0
T3 3835 3741 0 0
T4 889 770 0 0
T5 1783 1604 0 0
T10 2747 2658 0 0
T24 882 829 0 0
T25 2039 1962 0 0
T26 1178 1091 0 0
T27 1382 1295 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11881186 11681859 0 0
T1 1479 1387 0 0
T2 904 818 0 0
T3 3835 3741 0 0
T4 889 770 0 0
T5 1783 1604 0 0
T10 2747 2658 0 0
T24 882 829 0 0
T25 2039 1962 0 0
T26 1178 1091 0 0
T27 1382 1295 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 11669615 559847 0 0
T5 1783 109 0 0
T6 26706 0 0 0
T10 2747 1409 0 0
T11 0 2215 0 0
T12 0 148 0 0
T16 0 3245 0 0
T19 0 48 0 0
T24 882 0 0 0
T25 2039 0 0 0
T26 1178 0 0 0
T27 1382 0 0 0
T28 809 0 0 0
T29 1539 0 0 0
T31 0 7 0 0
T32 0 118 0 0
T37 1266 0 0 0
T62 0 1232 0 0
T70 0 132 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%