Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	133961	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

252056

1

T1

8

T2

8

T3

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	170626	1			T1	57		T2	20		T3	49
values[0x0]	101975	1			T1	2		T2	5		T3	6
values[0x1]	113416	1			T1	5		T2	4		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	90659	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

295358

1

T1

24

T2

14

T3

20

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1503	1			T73	1		T15	1		T27	1
valid_sources[0x01]	1340	1			T1	2		T3	1		T24	1
valid_sources[0x02]	2250	1			T1	1		T22	1		T24	3
valid_sources[0x03]	1646	1			T2	1		T3	1		T15	3
valid_sources[0x04]	1367	1			T15	2		T18	2		T38	1
valid_sources[0x05]	1536	1			T18	1		T129	1		T16	1
valid_sources[0x06]	1568	1			T15	3		T18	1		T7	2
valid_sources[0x07]	1594	1			T14	1		T15	1		T129	1
valid_sources[0x08]	1475	1			T3	1		T22	3		T15	1
valid_sources[0x09]	1790	1			T73	3		T14	1		T15	4
valid_sources[0x0a]	1637	1			T15	5		T129	2		T116	5
valid_sources[0x0b]	1536	1			T15	1		T39	2		T135	1
valid_sources[0x0c]	1645	1			T24	2		T15	2		T25	1
valid_sources[0x0d]	1243	1			T15	3		T18	2		T7	6
valid_sources[0x0e]	1353	1			T1	4		T73	1		T60	23
valid_sources[0x0f]	1492	1			T1	1		T22	3		T18	1
valid_sources[0x10]	1249	1			T10	8		T15	2		T18	1
valid_sources[0x11]	1307	1			T24	2		T15	3		T124	28
valid_sources[0x12]	1628	1			T1	3		T14	1		T15	3
valid_sources[0x13]	1314	1			T15	2		T16	3		T364	1
valid_sources[0x14]	1502	1			T1	2		T24	1		T15	3
valid_sources[0x15]	1479	1			T15	2		T69	1		T74	35
valid_sources[0x16]	1380	1			T3	2		T18	1		T129	1
valid_sources[0x17]	1342	1			T15	1		T53	5		T129	3
valid_sources[0x18]	1456	1			T22	2		T28	4		T14	1
valid_sources[0x19]	1384	1			T3	1		T14	9		T15	4
valid_sources[0x1a]	1773	1			T4	1		T5	487		T24	1
valid_sources[0x1b]	1710	1			T24	2		T14	2		T15	4
valid_sources[0x1c]	1556	1			T3	1		T24	2		T129	1
valid_sources[0x1d]	1447	1			T18	1		T135	2		T16	24
valid_sources[0x1e]	1328	1			T18	2		T129	2		T38	1
valid_sources[0x1f]	1903	1			T2	2		T22	2		T24	1
valid_sources[0x20]	1285	1			T24	1		T15	3		T25	1
valid_sources[0x21]	1390	1			T15	1		T18	1		T8	1
valid_sources[0x22]	1751	1			T22	5		T14	1		T15	4
valid_sources[0x23]	1668	1			T60	44		T15	3		T53	5
valid_sources[0x24]	1552	1			T4	1		T24	1		T15	1
valid_sources[0x25]	1212	1			T15	2		T18	1		T129	1
valid_sources[0x26]	2245	1			T25	1		T18	1		T129	1
valid_sources[0x27]	1162	1			T15	2		T84	3		T135	1
valid_sources[0x28]	1479	1			T24	1		T15	2		T129	1
valid_sources[0x29]	1358	1			T24	1		T15	1		T75	1
valid_sources[0x2a]	1199	1			T10	7		T15	1		T25	1
valid_sources[0x2b]	1535	1			T22	1		T129	1		T48	2
valid_sources[0x2c]	1230	1			T1	1		T53	1		T84	8
valid_sources[0x2d]	1403	1			T1	6		T14	2		T15	2
valid_sources[0x2e]	1263	1			T1	1		T73	2		T14	1
valid_sources[0x2f]	1351	1			T22	1		T15	2		T25	1
valid_sources[0x30]	1461	1			T3	1		T15	2		T27	1
valid_sources[0x31]	1234	1			T24	2		T15	1		T18	1
valid_sources[0x32]	1942	1			T1	2		T15	2		T129	2
valid_sources[0x33]	1495	1			T24	2		T15	1		T129	1
valid_sources[0x34]	1582	1			T15	1		T7	1		T129	1
valid_sources[0x35]	1450	1			T3	2		T22	1		T73	3
valid_sources[0x36]	1479	1			T129	4		T8	1		T116	1
valid_sources[0x37]	1426	1			T28	2		T41	5		T14	1
valid_sources[0x38]	1637	1			T1	1		T22	10		T14	1
valid_sources[0x39]	1750	1			T15	1		T26	1		T18	2
valid_sources[0x3a]	1992	1			T22	2		T15	2		T18	1
valid_sources[0x3b]	1477	1			T24	1		T15	2		T27	1
valid_sources[0x3c]	2300	1			T73	1		T18	1		T8	1
valid_sources[0x3d]	1822	1			T15	1		T18	1		T128	1
valid_sources[0x3e]	1803	1			T3	1		T22	1		T15	4
valid_sources[0x3f]	2081	1			T24	1		T18	1		T72	1
valid_sources[0x40]	1287	1			T1	1		T15	2		T129	1
valid_sources[0x41]	1073	1			T25	5		T18	1		T129	1
valid_sources[0x42]	1553	1			T15	1		T67	3		T25	1
valid_sources[0x43]	1417	1			T2	1		T3	1		T15	2
valid_sources[0x44]	1787	1			T73	5		T18	1		T129	1
valid_sources[0x45]	1225	1			T15	1		T7	3		T129	2
valid_sources[0x46]	1385	1			T24	1		T14	1		T15	5
valid_sources[0x47]	2583	1			T9	33		T73	1		T15	1
valid_sources[0x48]	1400	1			T10	39		T14	1		T15	1
valid_sources[0x49]	1505	1			T28	1		T15	1		T67	1
valid_sources[0x4a]	1284	1			T3	1		T73	1		T60	1
valid_sources[0x4b]	1244	1			T3	1		T73	2		T14	1
valid_sources[0x4c]	1521	1			T21	2		T15	1		T25	1
valid_sources[0x4d]	1428	1			T14	1		T15	1		T8	1
valid_sources[0x4e]	1219	1			T3	1		T15	2		T25	1
valid_sources[0x4f]	1312	1			T15	3		T25	1		T18	1
valid_sources[0x50]	1406	1			T3	1		T9	1		T15	1
valid_sources[0x51]	1493	1			T3	1		T129	1		T116	1
valid_sources[0x52]	1505	1			T15	4		T25	2		T18	1
valid_sources[0x53]	1439	1			T24	1		T14	1		T15	3
valid_sources[0x54]	1163	1			T15	1		T129	1		T75	1
valid_sources[0x55]	2088	1			T73	1		T15	1		T26	5
valid_sources[0x56]	1940	1			T3	1		T24	1		T14	2
valid_sources[0x57]	1100	1			T15	3		T27	1		T26	8
valid_sources[0x58]	1261	1			T1	4		T24	1		T28	1
valid_sources[0x59]	1161	1			T8	1		T16	15		T55	1
valid_sources[0x5a]	1332	1			T3	1		T22	1		T15	8
valid_sources[0x5b]	1834	1			T84	1		T116	7		T48	1
valid_sources[0x5c]	1471	1			T22	1		T15	3		T129	1
valid_sources[0x5d]	1359	1			T4	1		T18	1		T7	1
valid_sources[0x5e]	1272	1			T3	1		T22	1		T73	1
valid_sources[0x5f]	2492	1			T22	2		T15	2		T25	3
valid_sources[0x60]	1578	1			T73	1		T15	1		T18	1
valid_sources[0x61]	1409	1			T1	1		T3	1		T4	1
valid_sources[0x62]	1380	1			T3	2		T14	7		T15	3
valid_sources[0x63]	2012	1			T43	63		T24	1		T18	1
valid_sources[0x64]	1330	1			T14	1		T15	1		T25	1
valid_sources[0x65]	1581	1			T2	1		T3	1		T28	4
valid_sources[0x66]	1539	1			T1	7		T15	1		T25	1
valid_sources[0x67]	1252	1			T9	26		T15	1		T8	1
valid_sources[0x68]	1504	1			T4	1		T15	3		T18	1
valid_sources[0x69]	1690	1			T1	5		T3	2		T24	2
valid_sources[0x6a]	1588	1			T14	1		T15	3		T194	1
valid_sources[0x6b]	1386	1			T73	1		T15	1		T18	1
valid_sources[0x6c]	1376	1			T15	3		T18	2		T53	1
valid_sources[0x6d]	1522	1			T20	124		T14	2		T15	1
valid_sources[0x6e]	1234	1			T1	2		T73	2		T15	1
valid_sources[0x6f]	1417	1			T3	1		T14	2		T15	3
valid_sources[0x70]	1548	1			T24	1		T15	1		T129	2
valid_sources[0x71]	1540	1			T9	8		T18	1		T129	2
valid_sources[0x72]	1505	1			T60	4		T53	2		T84	2
valid_sources[0x73]	1240	1			T15	4		T63	1		T115	2
valid_sources[0x74]	1877	1			T15	2		T84	10		T8	1
valid_sources[0x75]	1389	1			T3	1		T4	1		T24	1
valid_sources[0x76]	2000	1			T3	1		T15	2		T75	1
valid_sources[0x77]	1391	1			T73	2		T15	1		T364	1
valid_sources[0x78]	1169	1			T24	1		T14	2		T15	1
valid_sources[0x79]	1257	1			T4	1		T15	3		T69	1
valid_sources[0x7a]	1997	1			T15	2		T129	1		T116	4
valid_sources[0x7b]	1562	1			T18	1		T7	3		T129	1
valid_sources[0x7c]	1228	1			T3	1		T73	1		T14	2
valid_sources[0x7d]	1236	1			T1	2		T3	1		T4	1
valid_sources[0x7e]	1285	1			T9	7		T73	1		T15	3
valid_sources[0x7f]	1346	1			T24	1		T28	2		T66	4
valid_sources[0x80]	2023	1			T3	2		T4	1		T15	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

68466

1

T1

4

T2

3

T3

3

values[0x0]

all_enables

biggest_size

92740

1

T2

4

T3

3

T20

18

values[0x1]

all_enables

biggest_size

90850

1

T1

4

T2

1

T3

1