Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	1643	1			T20	2		T9	2		T5	5
non_zero_bins[1]	1156	1			T20	1		T9	3		T5	2
zero	5621	1			T1	3		T2	3		T3	2

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	267	1			T5	1		T73	1		T60	2
uni	1929	1			T1	1		T2	1		T20	3
gen	2909	1			T1	1		T2	1		T3	1
res	639	1			T9	3		T10	5		T18	2
ins	2676	1			T1	1		T2	1		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

5281

1

T1

3

T2

3

T3

2

mubi_true

3139

1

T20

2

T21

1

T9

5

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

35

1

T14

1

T58

1

T138

1

pass

8385

1

T1

3

T2

3

T3

2

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	61	1			T61	1		T44	1		T134	1
upd	non_zero_bins[0]	pass	mubi_true	61	1			T115	1		T131	1		T134	1
upd	non_zero_bins[1]	pass	mubi_false	48	1			T5	1		T60	1		T117	1
upd	non_zero_bins[1]	pass	mubi_true	35	1			T116	2		T122	1		T83	1
upd	zero	pass	mubi_false	31	1			T73	1		T60	1		T134	1
upd	zero	pass	mubi_true	31	1			T118	1		T309	2		T310	1
uni	zero	pass	mubi_false	1456	1			T1	1		T2	1		T20	3
uni	zero	pass	mubi_true	473	1			T5	2		T43	1		T24	1
gen	non_zero_bins[0]	pass	mubi_false	320	1			T19	4		T129	1		T116	1
gen	non_zero_bins[0]	pass	mubi_true	339	1			T10	3		T60	2		T61	1
gen	non_zero_bins[1]	pass	mubi_false	251	1			T5	1		T73	1		T18	4
gen	non_zero_bins[1]	pass	mubi_true	209	1			T20	1		T60	1		T61	1
gen	zero	fail	mubi_false	29	1			T14	1		T58	1		T138	1
gen	zero	pass	mubi_false	1056	1			T1	1		T2	1		T3	1
gen	zero	pass	mubi_true	705	1			T20	1		T21	1		T22	2
res	non_zero_bins[0]	pass	mubi_false	174	1			T10	5		T18	2		T45	5
res	non_zero_bins[0]	pass	mubi_true	117	1			T53	3		T116	1		T91	2
res	non_zero_bins[1]	pass	mubi_false	108	1			T19	1		T38	2		T48	1
res	non_zero_bins[1]	pass	mubi_true	90	1			T9	3		T19	3		T115	1
res	zero	fail	mubi_false	6	1			T181	1		T95	1		T311	1
res	zero	pass	mubi_false	89	1			T61	1		T129	1		T49	1
res	zero	pass	mubi_true	55	1			T99	2		T260	1		T152	6
ins	non_zero_bins[0]	pass	mubi_false	305	1			T20	2		T5	2		T60	1
ins	non_zero_bins[0]	pass	mubi_true	266	1			T9	2		T5	3		T10	1
ins	non_zero_bins[1]	pass	mubi_false	192	1			T40	1		T45	1		T91	1
ins	non_zero_bins[1]	pass	mubi_true	223	1			T73	1		T60	2		T61	1
ins	zero	pass	mubi_false	1155	1			T1	1		T2	1		T3	1
ins	zero	pass	mubi_true	535	1			T22	2		T41	2		T14	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded