Module Definition
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Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.28 100.00 90.88 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.28 100.00 90.88 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.28 100.00 90.88 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.28 100.00 90.88 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.28 100.00 90.88 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.28 100.00 90.88 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.57 100.00 100.00 92.86 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.57 100.00 100.00 92.86 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.28 100.00 90.88 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00

Line Coverage for Module : edn_ack_sm
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00

51 52 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled) Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled): 52.1 `ifdef SIMULATION 52.2 prim_sparse_fsm_flop #( 52.3 .StateEnumT(state_e), 52.4 .Width($bits(state_e)), 52.5 .ResetValue($bits(state_e)'(Disabled)), 52.6 .EnableAlertTriggerSVA(1), 52.7 .CustomForceName("state_q") 52.8 ) u_state_regs ( 52.9 .clk_i ( clk_i ), 52.10 .rst_ni ( rst_ni ), 52.11 .state_i ( state_d ), 52.12 .state_o ( ) 52.13 ); 52.14 always_ff @(posedge clk_i or negedge rst_ni) begin 52.15 1/1 if (!rst_ni) begin Tests: T1 T2 T3  52.16 1/1 state_q <= Disabled; Tests: T1 T2 T3  52.17 end else begin 52.18 1/1 state_q <= state_d; Tests: T1 T2 T3  52.19 end 52.20 end 52.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o)) 52.22 else begin 52.23 `ifdef UVM 52.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 52.25 "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1); 52.26 `else 52.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__, 52.28 `PRIM_STRINGIFY(u_state_regs_A)); 52.29 `endif 52.30 end 52.31 `else 52.32 prim_sparse_fsm_flop #( 52.33 .StateEnumT(state_e), 52.34 .Width($bits(state_e)), 52.35 .ResetValue($bits(state_e)'(Disabled)), 52.36 .EnableAlertTriggerSVA(1) 52.37 ) u_state_regs ( 52.38 .clk_i ( `PRIM_FLOP_CLK ), 52.39 .rst_ni ( `PRIM_FLOP_RST ), 52.40 .state_i ( state_d ), 52.41 .state_o ( state_q ) 52.42 ); 52.43 `endif53 54 always_comb begin 55 1/1 state_d = state_q; Tests: T1 T2 T3  56 1/1 ack_o = 1'b0; Tests: T1 T2 T3  57 1/1 fifo_clr_o = 1'b0; Tests: T1 T2 T3  58 1/1 fifo_pop_o = 1'b0; Tests: T1 T2 T3  59 1/1 ack_sm_err_o = 1'b0; Tests: T1 T2 T3  60 1/1 unique case (state_q) Tests: T1 T2 T3  61 Disabled: begin 62 1/1 if (enable_i) begin Tests: T1 T2 T3  63 1/1 state_d = EndPointClear; Tests: T1 T2 T3  64 1/1 fifo_clr_o = 1'b1; Tests: T1 T2 T3  65 end MISSING_ELSE 66 end 67 EndPointClear: begin 68 1/1 state_d = Idle; Tests: T1 T2 T3  69 end 70 Idle: begin 71 1/1 if (req_i) begin Tests: T1 T2 T3  72 1/1 if (fifo_not_empty_i) begin Tests: T1 T2 T3  73 1/1 fifo_pop_o = 1'b1; Tests: T1 T2 T3  74 end MISSING_ELSE 75 1/1 state_d = DataWait; Tests: T1 T2 T3  76 end MISSING_ELSE 77 end 78 DataWait: begin 79 1/1 if (fifo_not_empty_i) begin Tests: T1 T2 T3  80 1/1 state_d = AckPls; Tests: T1 T2 T3  81 end MISSING_ELSE 82 end 83 AckPls: begin 84 1/1 ack_o = 1'b1; Tests: T1 T2 T3  85 1/1 state_d = Idle; Tests: T1 T2 T3  86 end 87 Error: begin 88 1/1 ack_sm_err_o = 1'b1; Tests: T3 T4 T28  89 end 90 default: begin 91 ack_sm_err_o = 1'b1; 92 state_d = Error; 93 end 94 endcase // unique case (state_q) 95 96 // If local escalation is seen, transition directly to 97 // error state. 98 1/1 if (local_escalate_i) begin Tests: T1 T2 T3  99 1/1 state_d = Error; Tests: T3 T4 T28  100 // Tie off outputs, except for ack_sm_err_o. 101 1/1 ack_o = 1'b0; Tests: T3 T4 T28  102 1/1 fifo_clr_o = 1'b0; Tests: T3 T4 T28  103 1/1 fifo_pop_o = 1'b0; Tests: T3 T4 T28  104 1/1 end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin Tests: T1 T2 T3  105 // Only disable if state is legal and not Disabled or Error. 106 // Even when disabled, illegal states must result in a transition to Error. 107 1/1 state_d = Disabled; Tests: T21 T4 T9  108 // Tie off all outputs, except for ack_sm_err_o. 109 1/1 ack_o = 1'b0; Tests: T21 T4 T9  110 1/1 fifo_pop_o = 1'b0; Tests: T21 T4 T9  111 1/1 fifo_clr_o = 1'b0; Tests: T21 T4 T9  112 end MISSING_ELSE

Cond Coverage for Module : edn_ack_sm
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT21,T4,T9

FSM Coverage for Module : edn_ack_sm
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 13 92.86
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
AckPls 80 Covered T1,T2,T3
DataWait 75 Covered T1,T2,T3
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T3,T4,T28
Idle 68 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
AckPls->Disabled 107 Covered T214
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T1,T2,T3
DataWait->AckPls 80 Covered T1,T2,T3
DataWait->Disabled 107 Covered T21,T19,T47
DataWait->Error 99 Covered T6,T68,T7
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T15,T16,T17
EndPointClear->Disabled 107 Covered T129,T96,T116
EndPointClear->Error 99 Covered T4,T15,T16
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T1,T2,T3
Idle->Disabled 107 Covered T21,T4,T9
Idle->Error 99 Covered T3,T28,T6



Branch Coverage for Module : edn_ack_sm
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00


52 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled) -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


60 unique case (state_q) -1- 61 Disabled: begin 62 if (enable_i) begin -2- 63 state_d = EndPointClear; ==> 64 fifo_clr_o = 1'b1; 65 end MISSING_ELSE ==> 66 end 67 EndPointClear: begin 68 state_d = Idle; ==> 69 end 70 Idle: begin 71 if (req_i) begin -3- 72 if (fifo_not_empty_i) begin -4- 73 fifo_pop_o = 1'b1; ==> 74 end MISSING_ELSE ==> 75 state_d = DataWait; 76 end MISSING_ELSE ==> 77 end 78 DataWait: begin 79 if (fifo_not_empty_i) begin -5- 80 state_d = AckPls; ==> 81 end MISSING_ELSE ==> 82 end 83 AckPls: begin 84 ack_o = 1'b1; ==> 85 state_d = Idle; 86 end 87 Error: begin 88 ack_sm_err_o = 1'b1; ==> 89 end 90 default: begin 91 ack_sm_err_o = 1'b1; ==>

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T1,T2,T3
Idle - 1 0 - Covered T1,T2,T3
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T1,T2,T3
DataWait - - - 0 Covered T1,T2,T20
AckPls - - - - Covered T1,T2,T3
Error - - - - Covered T3,T4,T28
default - - - - Covered T3,T28,T15


98 if (local_escalate_i) begin -1- 99 state_d = Error; ==> 100 // Tie off outputs, except for ack_sm_err_o. 101 ack_o = 1'b0; 102 fifo_clr_o = 1'b0; 103 fifo_pop_o = 1'b0; 104 end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin -2- 105 // Only disable if state is legal and not Disabled or Error. 106 // Even when disabled, illegal states must result in a transition to Error. 107 state_d = Disabled; ==> 108 // Tie off all outputs, except for ack_sm_err_o. 109 ack_o = 1'b0; 110 fifo_pop_o = 1'b0; 111 fifo_clr_o = 1'b0; 112 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T3,T4,T28
0 1 Covered T21,T4,T9
0 0 Covered T1,T2,T3


Assert Coverage for Module : edn_ack_sm
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
AckSmErrorStStable_A 64248807 1081646 0 0
FpvSecCmErrorStEscalate_A 64248807 1088961 0 0
u_state_regs_A 64207563 62960849 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 64248807 1081646 0 0
T3 6055 2456 0 0
T4 12460 7490 0 0
T5 53704 0 0 0
T6 0 8246 0 0
T7 0 1890 0 0
T8 0 2303 0 0
T9 11928 0 0 0
T15 0 74865 0 0
T20 31976 0 0 0
T21 7882 0 0 0
T22 14812 0 0 0
T23 8631 0 0 0
T24 6930 0 0 0
T28 0 4010 0 0
T43 10962 0 0 0
T68 0 3409 0 0
T74 0 7833 0 0
T75 0 1910 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 64248807 1088961 0 0
T3 6055 2463 0 0
T4 12460 7497 0 0
T5 53704 0 0 0
T6 0 8253 0 0
T7 0 1897 0 0
T8 0 2310 0 0
T9 11928 0 0 0
T15 0 75775 0 0
T20 31976 0 0 0
T21 7882 0 0 0
T22 14812 0 0 0
T23 8631 0 0 0
T24 6930 0 0 0
T28 0 4017 0 0
T43 10962 0 0 0
T68 0 3416 0 0
T74 0 7840 0 0
T75 0 1917 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 64207563 62960849 0 0
T1 8211 7609 0 0
T2 9450 8820 0 0
T3 5943 4704 0 0
T4 12340 11318 0 0
T5 53704 50183 0 0
T9 11928 11389 0 0
T20 31976 31367 0 0
T21 7882 7252 0 0
T22 14812 14126 0 0
T23 8631 8246 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00

51 52 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled) Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled): 52.1 `ifdef SIMULATION 52.2 prim_sparse_fsm_flop #( 52.3 .StateEnumT(state_e), 52.4 .Width($bits(state_e)), 52.5 .ResetValue($bits(state_e)'(Disabled)), 52.6 .EnableAlertTriggerSVA(1), 52.7 .CustomForceName("state_q") 52.8 ) u_state_regs ( 52.9 .clk_i ( clk_i ), 52.10 .rst_ni ( rst_ni ), 52.11 .state_i ( state_d ), 52.12 .state_o ( ) 52.13 ); 52.14 always_ff @(posedge clk_i or negedge rst_ni) begin 52.15 1/1 if (!rst_ni) begin Tests: T1 T2 T3  52.16 1/1 state_q <= Disabled; Tests: T1 T2 T3  52.17 end else begin 52.18 1/1 state_q <= state_d; Tests: T1 T2 T3  52.19 end 52.20 end 52.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o)) 52.22 else begin 52.23 `ifdef UVM 52.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 52.25 "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1); 52.26 `else 52.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__, 52.28 `PRIM_STRINGIFY(u_state_regs_A)); 52.29 `endif 52.30 end 52.31 `else 52.32 prim_sparse_fsm_flop #( 52.33 .StateEnumT(state_e), 52.34 .Width($bits(state_e)), 52.35 .ResetValue($bits(state_e)'(Disabled)), 52.36 .EnableAlertTriggerSVA(1) 52.37 ) u_state_regs ( 52.38 .clk_i ( `PRIM_FLOP_CLK ), 52.39 .rst_ni ( `PRIM_FLOP_RST ), 52.40 .state_i ( state_d ), 52.41 .state_o ( state_q ) 52.42 ); 52.43 `endif53 54 always_comb begin 55 1/1 state_d = state_q; Tests: T1 T2 T3  56 1/1 ack_o = 1'b0; Tests: T1 T2 T3  57 1/1 fifo_clr_o = 1'b0; Tests: T1 T2 T3  58 1/1 fifo_pop_o = 1'b0; Tests: T1 T2 T3  59 1/1 ack_sm_err_o = 1'b0; Tests: T1 T2 T3  60 1/1 unique case (state_q) Tests: T1 T2 T3  61 Disabled: begin 62 1/1 if (enable_i) begin Tests: T1 T2 T3  63 1/1 state_d = EndPointClear; Tests: T1 T2 T3  64 1/1 fifo_clr_o = 1'b1; Tests: T1 T2 T3  65 end MISSING_ELSE 66 end 67 EndPointClear: begin 68 1/1 state_d = Idle; Tests: T1 T2 T3  69 end 70 Idle: begin 71 1/1 if (req_i) begin Tests: T1 T2 T3  72 1/1 if (fifo_not_empty_i) begin Tests: T21 T22 T27  73 1/1 fifo_pop_o = 1'b1; Tests: T21 T22 T27  74 end MISSING_ELSE 75 1/1 state_d = DataWait; Tests: T21 T22 T27  76 end MISSING_ELSE 77 end 78 DataWait: begin 79 1/1 if (fifo_not_empty_i) begin Tests: T21 T22 T27  80 1/1 state_d = AckPls; Tests: T21 T22 T27  81 end MISSING_ELSE 82 end 83 AckPls: begin 84 1/1 ack_o = 1'b1; Tests: T21 T22 T27  85 1/1 state_d = Idle; Tests: T21 T22 T27  86 end 87 Error: begin 88 1/1 ack_sm_err_o = 1'b1; Tests: T3 T4 T28  89 end 90 default: begin 91 ack_sm_err_o = 1'b1; 92 state_d = Error; 93 end 94 endcase // unique case (state_q) 95 96 // If local escalation is seen, transition directly to 97 // error state. 98 1/1 if (local_escalate_i) begin Tests: T1 T2 T3  99 1/1 state_d = Error; Tests: T3 T4 T28  100 // Tie off outputs, except for ack_sm_err_o. 101 1/1 ack_o = 1'b0; Tests: T3 T4 T28  102 1/1 fifo_clr_o = 1'b0; Tests: T3 T4 T28  103 1/1 fifo_pop_o = 1'b0; Tests: T3 T4 T28  104 1/1 end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin Tests: T1 T2 T3  105 // Only disable if state is legal and not Disabled or Error. 106 // Even when disabled, illegal states must result in a transition to Error. 107 1/1 state_d = Disabled; Tests: T21 T4 T9  108 // Tie off all outputs, except for ack_sm_err_o. 109 1/1 ack_o = 1'b0; Tests: T21 T4 T9  110 1/1 fifo_pop_o = 1'b0; Tests: T21 T4 T9  111 1/1 fifo_clr_o = 1'b0; Tests: T21 T4 T9  112 end MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT21,T4,T9

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 12 85.71
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
AckPls 80 Covered T21,T22,T27
DataWait 75 Covered T21,T22,T27
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T3,T4,T28
Idle 68 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
AckPls->Disabled 107 Not Covered
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T21,T22,T27
DataWait->AckPls 80 Covered T21,T22,T27
DataWait->Disabled 107 Covered T21,T19,T148
DataWait->Error 99 Covered T59,T65,T221
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T15,T16,T17
EndPointClear->Disabled 107 Covered T129,T96,T116
EndPointClear->Error 99 Covered T4,T15,T16
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T21,T22,T27
Idle->Disabled 107 Covered T4,T9,T22
Idle->Error 99 Covered T3,T28,T6



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00


52 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled) -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


60 unique case (state_q) -1- 61 Disabled: begin 62 if (enable_i) begin -2- 63 state_d = EndPointClear; ==> 64 fifo_clr_o = 1'b1; 65 end MISSING_ELSE ==> 66 end 67 EndPointClear: begin 68 state_d = Idle; ==> 69 end 70 Idle: begin 71 if (req_i) begin -3- 72 if (fifo_not_empty_i) begin -4- 73 fifo_pop_o = 1'b1; ==> 74 end MISSING_ELSE ==> 75 state_d = DataWait; 76 end MISSING_ELSE ==> 77 end 78 DataWait: begin 79 if (fifo_not_empty_i) begin -5- 80 state_d = AckPls; ==> 81 end MISSING_ELSE ==> 82 end 83 AckPls: begin 84 ack_o = 1'b1; ==> 85 state_d = Idle; 86 end 87 Error: begin 88 ack_sm_err_o = 1'b1; ==> 89 end 90 default: begin 91 ack_sm_err_o = 1'b1; ==>

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T21,T22,T27
Idle - 1 0 - Covered T21,T22,T27
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T21,T22,T27
DataWait - - - 0 Covered T21,T22,T18
AckPls - - - - Covered T21,T22,T27
Error - - - - Covered T3,T4,T28
default - - - - Covered T15,T16,T17


98 if (local_escalate_i) begin -1- 99 state_d = Error; ==> 100 // Tie off outputs, except for ack_sm_err_o. 101 ack_o = 1'b0; 102 fifo_clr_o = 1'b0; 103 fifo_pop_o = 1'b0; 104 end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin -2- 105 // Only disable if state is legal and not Disabled or Error. 106 // Even when disabled, illegal states must result in a transition to Error. 107 state_d = Disabled; ==> 108 // Tie off all outputs, except for ack_sm_err_o. 109 ack_o = 1'b0; 110 fifo_pop_o = 1'b0; 111 fifo_clr_o = 1'b0; 112 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T3,T4,T28
0 1 Covered T21,T4,T9
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
AckSmErrorStStable_A 9178401 154828 0 0
FpvSecCmErrorStEscalate_A 9178401 155873 0 0
u_state_regs_A 9178401 9000299 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9178401 154828 0 0
T3 865 358 0 0
T4 1780 1070 0 0
T5 7672 0 0 0
T6 0 1178 0 0
T7 0 270 0 0
T8 0 329 0 0
T9 1704 0 0 0
T15 0 10695 0 0
T20 4568 0 0 0
T21 1126 0 0 0
T22 2116 0 0 0
T23 1233 0 0 0
T24 990 0 0 0
T28 0 580 0 0
T43 1566 0 0 0
T68 0 487 0 0
T74 0 1119 0 0
T75 0 280 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9178401 155873 0 0
T3 865 359 0 0
T4 1780 1071 0 0
T5 7672 0 0 0
T6 0 1179 0 0
T7 0 271 0 0
T8 0 330 0 0
T9 1704 0 0 0
T15 0 10825 0 0
T20 4568 0 0 0
T21 1126 0 0 0
T22 2116 0 0 0
T23 1233 0 0 0
T24 990 0 0 0
T28 0 581 0 0
T43 1566 0 0 0
T68 0 488 0 0
T74 0 1120 0 0
T75 0 281 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9178401 9000299 0 0
T1 1173 1087 0 0
T2 1350 1260 0 0
T3 865 688 0 0
T4 1780 1634 0 0
T5 7672 7169 0 0
T9 1704 1627 0 0
T20 4568 4481 0 0
T21 1126 1036 0 0
T22 2116 2018 0 0
T23 1233 1178 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00

51 52 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled) Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled): 52.1 `ifdef SIMULATION 52.2 prim_sparse_fsm_flop #( 52.3 .StateEnumT(state_e), 52.4 .Width($bits(state_e)), 52.5 .ResetValue($bits(state_e)'(Disabled)), 52.6 .EnableAlertTriggerSVA(1), 52.7 .CustomForceName("state_q") 52.8 ) u_state_regs ( 52.9 .clk_i ( clk_i ), 52.10 .rst_ni ( rst_ni ), 52.11 .state_i ( state_d ), 52.12 .state_o ( ) 52.13 ); 52.14 always_ff @(posedge clk_i or negedge rst_ni) begin 52.15 1/1 if (!rst_ni) begin Tests: T1 T2 T3  52.16 1/1 state_q <= Disabled; Tests: T1 T2 T3  52.17 end else begin 52.18 1/1 state_q <= state_d; Tests: T1 T2 T3  52.19 end 52.20 end 52.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o)) 52.22 else begin 52.23 `ifdef UVM 52.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 52.25 "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1); 52.26 `else 52.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__, 52.28 `PRIM_STRINGIFY(u_state_regs_A)); 52.29 `endif 52.30 end 52.31 `else 52.32 prim_sparse_fsm_flop #( 52.33 .StateEnumT(state_e), 52.34 .Width($bits(state_e)), 52.35 .ResetValue($bits(state_e)'(Disabled)), 52.36 .EnableAlertTriggerSVA(1) 52.37 ) u_state_regs ( 52.38 .clk_i ( `PRIM_FLOP_CLK ), 52.39 .rst_ni ( `PRIM_FLOP_RST ), 52.40 .state_i ( state_d ), 52.41 .state_o ( state_q ) 52.42 ); 52.43 `endif53 54 always_comb begin 55 1/1 state_d = state_q; Tests: T1 T2 T3  56 1/1 ack_o = 1'b0; Tests: T1 T2 T3  57 1/1 fifo_clr_o = 1'b0; Tests: T1 T2 T3  58 1/1 fifo_pop_o = 1'b0; Tests: T1 T2 T3  59 1/1 ack_sm_err_o = 1'b0; Tests: T1 T2 T3  60 1/1 unique case (state_q) Tests: T1 T2 T3  61 Disabled: begin 62 1/1 if (enable_i) begin Tests: T1 T2 T3  63 1/1 state_d = EndPointClear; Tests: T1 T2 T3  64 1/1 fifo_clr_o = 1'b1; Tests: T1 T2 T3  65 end MISSING_ELSE 66 end 67 EndPointClear: begin 68 1/1 state_d = Idle; Tests: T1 T2 T3  69 end 70 Idle: begin 71 1/1 if (req_i) begin Tests: T1 T2 T3  72 1/1 if (fifo_not_empty_i) begin Tests: T26 T38 T45  73 1/1 fifo_pop_o = 1'b1; Tests: T26 T38 T45  74 end MISSING_ELSE 75 1/1 state_d = DataWait; Tests: T26 T38 T45  76 end MISSING_ELSE 77 end 78 DataWait: begin 79 1/1 if (fifo_not_empty_i) begin Tests: T26 T38 T45  80 1/1 state_d = AckPls; Tests: T26 T38 T45  81 end MISSING_ELSE 82 end 83 AckPls: begin 84 1/1 ack_o = 1'b1; Tests: T26 T38 T45  85 1/1 state_d = Idle; Tests: T26 T38 T45  86 end 87 Error: begin 88 1/1 ack_sm_err_o = 1'b1; Tests: T3 T4 T28  89 end 90 default: begin 91 ack_sm_err_o = 1'b1; 92 state_d = Error; 93 end 94 endcase // unique case (state_q) 95 96 // If local escalation is seen, transition directly to 97 // error state. 98 1/1 if (local_escalate_i) begin Tests: T1 T2 T3  99 1/1 state_d = Error; Tests: T3 T4 T28  100 // Tie off outputs, except for ack_sm_err_o. 101 1/1 ack_o = 1'b0; Tests: T3 T4 T28  102 1/1 fifo_clr_o = 1'b0; Tests: T3 T4 T28  103 1/1 fifo_pop_o = 1'b0; Tests: T3 T4 T28  104 1/1 end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin Tests: T1 T2 T3  105 // Only disable if state is legal and not Disabled or Error. 106 // Even when disabled, illegal states must result in a transition to Error. 107 1/1 state_d = Disabled; Tests: T21 T4 T9  108 // Tie off all outputs, except for ack_sm_err_o. 109 1/1 ack_o = 1'b0; Tests: T21 T4 T9  110 1/1 fifo_pop_o = 1'b0; Tests: T21 T4 T9  111 1/1 fifo_clr_o = 1'b0; Tests: T21 T4 T9  112 end MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT21,T4,T9

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 12 85.71
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
AckPls 80 Covered T26,T38,T45
DataWait 75 Covered T26,T38,T45
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T3,T4,T28
Idle 68 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
AckPls->Disabled 107 Not Covered
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T26,T38,T45
DataWait->AckPls 80 Covered T26,T38,T45
DataWait->Disabled 107 Covered T224,T225,T226
DataWait->Error 99 Covered T186,T227,T228
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T15,T16,T17
EndPointClear->Disabled 107 Covered T129,T96,T116
EndPointClear->Error 99 Covered T4,T15,T16
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T26,T38,T45
Idle->Disabled 107 Covered T21,T4,T9
Idle->Error 99 Covered T3,T28,T6



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00


52 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled) -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


60 unique case (state_q) -1- 61 Disabled: begin 62 if (enable_i) begin -2- 63 state_d = EndPointClear; ==> 64 fifo_clr_o = 1'b1; 65 end MISSING_ELSE ==> 66 end 67 EndPointClear: begin 68 state_d = Idle; ==> 69 end 70 Idle: begin 71 if (req_i) begin -3- 72 if (fifo_not_empty_i) begin -4- 73 fifo_pop_o = 1'b1; ==> 74 end MISSING_ELSE ==> 75 state_d = DataWait; 76 end MISSING_ELSE ==> 77 end 78 DataWait: begin 79 if (fifo_not_empty_i) begin -5- 80 state_d = AckPls; ==> 81 end MISSING_ELSE ==> 82 end 83 AckPls: begin 84 ack_o = 1'b1; ==> 85 state_d = Idle; 86 end 87 Error: begin 88 ack_sm_err_o = 1'b1; ==> 89 end 90 default: begin 91 ack_sm_err_o = 1'b1; ==>

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T26,T38,T45
Idle - 1 0 - Covered T26,T38,T45
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T26,T38,T45
DataWait - - - 0 Covered T38,T45,T44
AckPls - - - - Covered T26,T38,T45
Error - - - - Covered T3,T4,T28
default - - - - Covered T15,T16,T17


98 if (local_escalate_i) begin -1- 99 state_d = Error; ==> 100 // Tie off outputs, except for ack_sm_err_o. 101 ack_o = 1'b0; 102 fifo_clr_o = 1'b0; 103 fifo_pop_o = 1'b0; 104 end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin -2- 105 // Only disable if state is legal and not Disabled or Error. 106 // Even when disabled, illegal states must result in a transition to Error. 107 state_d = Disabled; ==> 108 // Tie off all outputs, except for ack_sm_err_o. 109 ack_o = 1'b0; 110 fifo_pop_o = 1'b0; 111 fifo_clr_o = 1'b0; 112 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T3,T4,T28
0 1 Covered T21,T4,T9
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
AckSmErrorStStable_A 9178401 154828 0 0
FpvSecCmErrorStEscalate_A 9178401 155873 0 0
u_state_regs_A 9178401 9000299 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9178401 154828 0 0
T3 865 358 0 0
T4 1780 1070 0 0
T5 7672 0 0 0
T6 0 1178 0 0
T7 0 270 0 0
T8 0 329 0 0
T9 1704 0 0 0
T15 0 10695 0 0
T20 4568 0 0 0
T21 1126 0 0 0
T22 2116 0 0 0
T23 1233 0 0 0
T24 990 0 0 0
T28 0 580 0 0
T43 1566 0 0 0
T68 0 487 0 0
T74 0 1119 0 0
T75 0 280 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9178401 155873 0 0
T3 865 359 0 0
T4 1780 1071 0 0
T5 7672 0 0 0
T6 0 1179 0 0
T7 0 271 0 0
T8 0 330 0 0
T9 1704 0 0 0
T15 0 10825 0 0
T20 4568 0 0 0
T21 1126 0 0 0
T22 2116 0 0 0
T23 1233 0 0 0
T24 990 0 0 0
T28 0 581 0 0
T43 1566 0 0 0
T68 0 488 0 0
T74 0 1120 0 0
T75 0 281 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9178401 9000299 0 0
T1 1173 1087 0 0
T2 1350 1260 0 0
T3 865 688 0 0
T4 1780 1634 0 0
T5 7672 7169 0 0
T9 1704 1627 0 0
T20 4568 4481 0 0
T21 1126 1036 0 0
T22 2116 2018 0 0
T23 1233 1178 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00

51 52 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled) Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled): 52.1 `ifdef SIMULATION 52.2 prim_sparse_fsm_flop #( 52.3 .StateEnumT(state_e), 52.4 .Width($bits(state_e)), 52.5 .ResetValue($bits(state_e)'(Disabled)), 52.6 .EnableAlertTriggerSVA(1), 52.7 .CustomForceName("state_q") 52.8 ) u_state_regs ( 52.9 .clk_i ( clk_i ), 52.10 .rst_ni ( rst_ni ), 52.11 .state_i ( state_d ), 52.12 .state_o ( ) 52.13 ); 52.14 always_ff @(posedge clk_i or negedge rst_ni) begin 52.15 1/1 if (!rst_ni) begin Tests: T1 T2 T3  52.16 1/1 state_q <= Disabled; Tests: T1 T2 T3  52.17 end else begin 52.18 1/1 state_q <= state_d; Tests: T1 T2 T3  52.19 end 52.20 end 52.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o)) 52.22 else begin 52.23 `ifdef UVM 52.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 52.25 "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1); 52.26 `else 52.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__, 52.28 `PRIM_STRINGIFY(u_state_regs_A)); 52.29 `endif 52.30 end 52.31 `else 52.32 prim_sparse_fsm_flop #( 52.33 .StateEnumT(state_e), 52.34 .Width($bits(state_e)), 52.35 .ResetValue($bits(state_e)'(Disabled)), 52.36 .EnableAlertTriggerSVA(1) 52.37 ) u_state_regs ( 52.38 .clk_i ( `PRIM_FLOP_CLK ), 52.39 .rst_ni ( `PRIM_FLOP_RST ), 52.40 .state_i ( state_d ), 52.41 .state_o ( state_q ) 52.42 ); 52.43 `endif53 54 always_comb begin 55 1/1 state_d = state_q; Tests: T1 T2 T3  56 1/1 ack_o = 1'b0; Tests: T1 T2 T3  57 1/1 fifo_clr_o = 1'b0; Tests: T1 T2 T3  58 1/1 fifo_pop_o = 1'b0; Tests: T1 T2 T3  59 1/1 ack_sm_err_o = 1'b0; Tests: T1 T2 T3  60 1/1 unique case (state_q) Tests: T1 T2 T3  61 Disabled: begin 62 1/1 if (enable_i) begin Tests: T1 T2 T3  63 1/1 state_d = EndPointClear; Tests: T1 T2 T3  64 1/1 fifo_clr_o = 1'b1; Tests: T1 T2 T3  65 end MISSING_ELSE 66 end 67 EndPointClear: begin 68 1/1 state_d = Idle; Tests: T1 T2 T3  69 end 70 Idle: begin 71 1/1 if (req_i) begin Tests: T1 T2 T3  72 1/1 if (fifo_not_empty_i) begin Tests: T22 T39 T18  73 1/1 fifo_pop_o = 1'b1; Tests: T22 T39 T18  74 end MISSING_ELSE 75 1/1 state_d = DataWait; Tests: T22 T39 T18  76 end MISSING_ELSE 77 end 78 DataWait: begin 79 1/1 if (fifo_not_empty_i) begin Tests: T22 T39 T18  80 1/1 state_d = AckPls; Tests: T22 T39 T18  81 end MISSING_ELSE 82 end 83 AckPls: begin 84 1/1 ack_o = 1'b1; Tests: T22 T39 T18  85 1/1 state_d = Idle; Tests: T22 T39 T18  86 end 87 Error: begin 88 1/1 ack_sm_err_o = 1'b1; Tests: T3 T4 T28  89 end 90 default: begin 91 ack_sm_err_o = 1'b1; 92 state_d = Error; 93 end 94 endcase // unique case (state_q) 95 96 // If local escalation is seen, transition directly to 97 // error state. 98 1/1 if (local_escalate_i) begin Tests: T1 T2 T3  99 1/1 state_d = Error; Tests: T3 T4 T28  100 // Tie off outputs, except for ack_sm_err_o. 101 1/1 ack_o = 1'b0; Tests: T3 T4 T28  102 1/1 fifo_clr_o = 1'b0; Tests: T3 T4 T28  103 1/1 fifo_pop_o = 1'b0; Tests: T3 T4 T28  104 1/1 end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin Tests: T1 T2 T3  105 // Only disable if state is legal and not Disabled or Error. 106 // Even when disabled, illegal states must result in a transition to Error. 107 1/1 state_d = Disabled; Tests: T21 T4 T9  108 // Tie off all outputs, except for ack_sm_err_o. 109 1/1 ack_o = 1'b0; Tests: T21 T4 T9  110 1/1 fifo_pop_o = 1'b0; Tests: T21 T4 T9  111 1/1 fifo_clr_o = 1'b0; Tests: T21 T4 T9  112 end MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT21,T4,T9

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 12 85.71
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
AckPls 80 Covered T22,T39,T18
DataWait 75 Covered T22,T39,T18
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T3,T4,T28
Idle 68 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
AckPls->Disabled 107 Not Covered
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T22,T39,T18
DataWait->AckPls 80 Covered T22,T39,T18
DataWait->Disabled 107 Covered T47,T172,T90
DataWait->Error 99 Covered T185,T192,T229
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T15,T16,T17
EndPointClear->Disabled 107 Covered T129,T96,T116
EndPointClear->Error 99 Covered T4,T15,T16
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T22,T39,T18
Idle->Disabled 107 Covered T21,T4,T9
Idle->Error 99 Covered T3,T28,T6



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00


52 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled) -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


60 unique case (state_q) -1- 61 Disabled: begin 62 if (enable_i) begin -2- 63 state_d = EndPointClear; ==> 64 fifo_clr_o = 1'b1; 65 end MISSING_ELSE ==> 66 end 67 EndPointClear: begin 68 state_d = Idle; ==> 69 end 70 Idle: begin 71 if (req_i) begin -3- 72 if (fifo_not_empty_i) begin -4- 73 fifo_pop_o = 1'b1; ==> 74 end MISSING_ELSE ==> 75 state_d = DataWait; 76 end MISSING_ELSE ==> 77 end 78 DataWait: begin 79 if (fifo_not_empty_i) begin -5- 80 state_d = AckPls; ==> 81 end MISSING_ELSE ==> 82 end 83 AckPls: begin 84 ack_o = 1'b1; ==> 85 state_d = Idle; 86 end 87 Error: begin 88 ack_sm_err_o = 1'b1; ==> 89 end 90 default: begin 91 ack_sm_err_o = 1'b1; ==>

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T22,T39,T18
Idle - 1 0 - Covered T22,T39,T18
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T22,T39,T18
DataWait - - - 0 Covered T39,T18,T47
AckPls - - - - Covered T22,T39,T18
Error - - - - Covered T3,T4,T28
default - - - - Covered T15,T16,T17


98 if (local_escalate_i) begin -1- 99 state_d = Error; ==> 100 // Tie off outputs, except for ack_sm_err_o. 101 ack_o = 1'b0; 102 fifo_clr_o = 1'b0; 103 fifo_pop_o = 1'b0; 104 end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin -2- 105 // Only disable if state is legal and not Disabled or Error. 106 // Even when disabled, illegal states must result in a transition to Error. 107 state_d = Disabled; ==> 108 // Tie off all outputs, except for ack_sm_err_o. 109 ack_o = 1'b0; 110 fifo_pop_o = 1'b0; 111 fifo_clr_o = 1'b0; 112 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T3,T4,T28
0 1 Covered T21,T4,T9
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
AckSmErrorStStable_A 9178401 154828 0 0
FpvSecCmErrorStEscalate_A 9178401 155873 0 0
u_state_regs_A 9178401 9000299 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9178401 154828 0 0
T3 865 358 0 0
T4 1780 1070 0 0
T5 7672 0 0 0
T6 0 1178 0 0
T7 0 270 0 0
T8 0 329 0 0
T9 1704 0 0 0
T15 0 10695 0 0
T20 4568 0 0 0
T21 1126 0 0 0
T22 2116 0 0 0
T23 1233 0 0 0
T24 990 0 0 0
T28 0 580 0 0
T43 1566 0 0 0
T68 0 487 0 0
T74 0 1119 0 0
T75 0 280 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9178401 155873 0 0
T3 865 359 0 0
T4 1780 1071 0 0
T5 7672 0 0 0
T6 0 1179 0 0
T7 0 271 0 0
T8 0 330 0 0
T9 1704 0 0 0
T15 0 10825 0 0
T20 4568 0 0 0
T21 1126 0 0 0
T22 2116 0 0 0
T23 1233 0 0 0
T24 990 0 0 0
T28 0 581 0 0
T43 1566 0 0 0
T68 0 488 0 0
T74 0 1120 0 0
T75 0 281 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9178401 9000299 0 0
T1 1173 1087 0 0
T2 1350 1260 0 0
T3 865 688 0 0
T4 1780 1634 0 0
T5 7672 7169 0 0
T9 1704 1627 0 0
T20 4568 4481 0 0
T21 1126 1036 0 0
T22 2116 2018 0 0
T23 1233 1178 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00

51 52 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled) Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled): 52.1 `ifdef SIMULATION 52.2 prim_sparse_fsm_flop #( 52.3 .StateEnumT(state_e), 52.4 .Width($bits(state_e)), 52.5 .ResetValue($bits(state_e)'(Disabled)), 52.6 .EnableAlertTriggerSVA(1), 52.7 .CustomForceName("state_q") 52.8 ) u_state_regs ( 52.9 .clk_i ( clk_i ), 52.10 .rst_ni ( rst_ni ), 52.11 .state_i ( state_d ), 52.12 .state_o ( ) 52.13 ); 52.14 always_ff @(posedge clk_i or negedge rst_ni) begin 52.15 1/1 if (!rst_ni) begin Tests: T1 T2 T3  52.16 1/1 state_q <= Disabled; Tests: T1 T2 T3  52.17 end else begin 52.18 1/1 state_q <= state_d; Tests: T1 T2 T3  52.19 end 52.20 end 52.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o)) 52.22 else begin 52.23 `ifdef UVM 52.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 52.25 "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1); 52.26 `else 52.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__, 52.28 `PRIM_STRINGIFY(u_state_regs_A)); 52.29 `endif 52.30 end 52.31 `else 52.32 prim_sparse_fsm_flop #( 52.33 .StateEnumT(state_e), 52.34 .Width($bits(state_e)), 52.35 .ResetValue($bits(state_e)'(Disabled)), 52.36 .EnableAlertTriggerSVA(1) 52.37 ) u_state_regs ( 52.38 .clk_i ( `PRIM_FLOP_CLK ), 52.39 .rst_ni ( `PRIM_FLOP_RST ), 52.40 .state_i ( state_d ), 52.41 .state_o ( state_q ) 52.42 ); 52.43 `endif53 54 always_comb begin 55 1/1 state_d = state_q; Tests: T1 T2 T3  56 1/1 ack_o = 1'b0; Tests: T1 T2 T3  57 1/1 fifo_clr_o = 1'b0; Tests: T1 T2 T3  58 1/1 fifo_pop_o = 1'b0; Tests: T1 T2 T3  59 1/1 ack_sm_err_o = 1'b0; Tests: T1 T2 T3  60 1/1 unique case (state_q) Tests: T1 T2 T3  61 Disabled: begin 62 1/1 if (enable_i) begin Tests: T1 T2 T3  63 1/1 state_d = EndPointClear; Tests: T1 T2 T3  64 1/1 fifo_clr_o = 1'b1; Tests: T1 T2 T3  65 end MISSING_ELSE 66 end 67 EndPointClear: begin 68 1/1 state_d = Idle; Tests: T1 T2 T3  69 end 70 Idle: begin 71 1/1 if (req_i) begin Tests: T1 T2 T3  72 1/1 if (fifo_not_empty_i) begin Tests: T14 T40 T8  73 1/1 fifo_pop_o = 1'b1; Tests: T14 T40 T50  74 end MISSING_ELSE 75 1/1 state_d = DataWait; Tests: T14 T40 T8  76 end MISSING_ELSE 77 end 78 DataWait: begin 79 1/1 if (fifo_not_empty_i) begin Tests: T14 T40 T8  80 1/1 state_d = AckPls; Tests: T14 T40 T50  81 end MISSING_ELSE 82 end 83 AckPls: begin 84 1/1 ack_o = 1'b1; Tests: T14 T40 T50  85 1/1 state_d = Idle; Tests: T14 T40 T50  86 end 87 Error: begin 88 1/1 ack_sm_err_o = 1'b1; Tests: T3 T4 T28  89 end 90 default: begin 91 ack_sm_err_o = 1'b1; 92 state_d = Error; 93 end 94 endcase // unique case (state_q) 95 96 // If local escalation is seen, transition directly to 97 // error state. 98 1/1 if (local_escalate_i) begin Tests: T1 T2 T3  99 1/1 state_d = Error; Tests: T3 T4 T28  100 // Tie off outputs, except for ack_sm_err_o. 101 1/1 ack_o = 1'b0; Tests: T3 T4 T28  102 1/1 fifo_clr_o = 1'b0; Tests: T3 T4 T28  103 1/1 fifo_pop_o = 1'b0; Tests: T3 T4 T28  104 1/1 end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin Tests: T1 T2 T3  105 // Only disable if state is legal and not Disabled or Error. 106 // Even when disabled, illegal states must result in a transition to Error. 107 1/1 state_d = Disabled; Tests: T21 T4 T9  108 // Tie off all outputs, except for ack_sm_err_o. 109 1/1 ack_o = 1'b0; Tests: T21 T4 T9  110 1/1 fifo_pop_o = 1'b0; Tests: T21 T4 T9  111 1/1 fifo_clr_o = 1'b0; Tests: T21 T4 T9  112 end MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT21,T4,T9

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 12 85.71
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
AckPls 80 Covered T14,T40,T50
DataWait 75 Covered T14,T40,T8
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T3,T4,T28
Idle 68 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
AckPls->Disabled 107 Not Covered
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T14,T40,T50
DataWait->AckPls 80 Covered T14,T40,T50
DataWait->Disabled 107 Covered T50,T91,T173
DataWait->Error 99 Covered T8,T133,T230
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T15,T16,T17
EndPointClear->Disabled 107 Covered T129,T96,T116
EndPointClear->Error 99 Covered T4,T15,T16
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T14,T40,T8
Idle->Disabled 107 Covered T21,T4,T9
Idle->Error 99 Covered T3,T28,T6



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00


52 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled) -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


60 unique case (state_q) -1- 61 Disabled: begin 62 if (enable_i) begin -2- 63 state_d = EndPointClear; ==> 64 fifo_clr_o = 1'b1; 65 end MISSING_ELSE ==> 66 end 67 EndPointClear: begin 68 state_d = Idle; ==> 69 end 70 Idle: begin 71 if (req_i) begin -3- 72 if (fifo_not_empty_i) begin -4- 73 fifo_pop_o = 1'b1; ==> 74 end MISSING_ELSE ==> 75 state_d = DataWait; 76 end MISSING_ELSE ==> 77 end 78 DataWait: begin 79 if (fifo_not_empty_i) begin -5- 80 state_d = AckPls; ==> 81 end MISSING_ELSE ==> 82 end 83 AckPls: begin 84 ack_o = 1'b1; ==> 85 state_d = Idle; 86 end 87 Error: begin 88 ack_sm_err_o = 1'b1; ==> 89 end 90 default: begin 91 ack_sm_err_o = 1'b1; ==>

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T14,T40,T50
Idle - 1 0 - Covered T14,T40,T8
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T14,T40,T50
DataWait - - - 0 Covered T14,T40,T8
AckPls - - - - Covered T14,T40,T50
Error - - - - Covered T3,T4,T28
default - - - - Covered T15,T16,T17


98 if (local_escalate_i) begin -1- 99 state_d = Error; ==> 100 // Tie off outputs, except for ack_sm_err_o. 101 ack_o = 1'b0; 102 fifo_clr_o = 1'b0; 103 fifo_pop_o = 1'b0; 104 end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin -2- 105 // Only disable if state is legal and not Disabled or Error. 106 // Even when disabled, illegal states must result in a transition to Error. 107 state_d = Disabled; ==> 108 // Tie off all outputs, except for ack_sm_err_o. 109 ack_o = 1'b0; 110 fifo_pop_o = 1'b0; 111 fifo_clr_o = 1'b0; 112 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T3,T4,T28
0 1 Covered T21,T4,T9
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
AckSmErrorStStable_A 9178401 154828 0 0
FpvSecCmErrorStEscalate_A 9178401 155873 0 0
u_state_regs_A 9178401 9000299 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9178401 154828 0 0
T3 865 358 0 0
T4 1780 1070 0 0
T5 7672 0 0 0
T6 0 1178 0 0
T7 0 270 0 0
T8 0 329 0 0
T9 1704 0 0 0
T15 0 10695 0 0
T20 4568 0 0 0
T21 1126 0 0 0
T22 2116 0 0 0
T23 1233 0 0 0
T24 990 0 0 0
T28 0 580 0 0
T43 1566 0 0 0
T68 0 487 0 0
T74 0 1119 0 0
T75 0 280 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9178401 155873 0 0
T3 865 359 0 0
T4 1780 1071 0 0
T5 7672 0 0 0
T6 0 1179 0 0
T7 0 271 0 0
T8 0 330 0 0
T9 1704 0 0 0
T15 0 10825 0 0
T20 4568 0 0 0
T21 1126 0 0 0
T22 2116 0 0 0
T23 1233 0 0 0
T24 990 0 0 0
T28 0 581 0 0
T43 1566 0 0 0
T68 0 488 0 0
T74 0 1120 0 0
T75 0 281 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9178401 9000299 0 0
T1 1173 1087 0 0
T2 1350 1260 0 0
T3 865 688 0 0
T4 1780 1634 0 0
T5 7672 7169 0 0
T9 1704 1627 0 0
T20 4568 4481 0 0
T21 1126 1036 0 0
T22 2116 2018 0 0
T23 1233 1178 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00

51 52 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled) Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled): 52.1 `ifdef SIMULATION 52.2 prim_sparse_fsm_flop #( 52.3 .StateEnumT(state_e), 52.4 .Width($bits(state_e)), 52.5 .ResetValue($bits(state_e)'(Disabled)), 52.6 .EnableAlertTriggerSVA(1), 52.7 .CustomForceName("state_q") 52.8 ) u_state_regs ( 52.9 .clk_i ( clk_i ), 52.10 .rst_ni ( rst_ni ), 52.11 .state_i ( state_d ), 52.12 .state_o ( ) 52.13 ); 52.14 always_ff @(posedge clk_i or negedge rst_ni) begin 52.15 1/1 if (!rst_ni) begin Tests: T1 T2 T3  52.16 1/1 state_q <= Disabled; Tests: T1 T2 T3  52.17 end else begin 52.18 1/1 state_q <= state_d; Tests: T1 T2 T3  52.19 end 52.20 end 52.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o)) 52.22 else begin 52.23 `ifdef UVM 52.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 52.25 "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1); 52.26 `else 52.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__, 52.28 `PRIM_STRINGIFY(u_state_regs_A)); 52.29 `endif 52.30 end 52.31 `else 52.32 prim_sparse_fsm_flop #( 52.33 .StateEnumT(state_e), 52.34 .Width($bits(state_e)), 52.35 .ResetValue($bits(state_e)'(Disabled)), 52.36 .EnableAlertTriggerSVA(1) 52.37 ) u_state_regs ( 52.38 .clk_i ( `PRIM_FLOP_CLK ), 52.39 .rst_ni ( `PRIM_FLOP_RST ), 52.40 .state_i ( state_d ), 52.41 .state_o ( state_q ) 52.42 ); 52.43 `endif53 54 always_comb begin 55 1/1 state_d = state_q; Tests: T1 T2 T3  56 1/1 ack_o = 1'b0; Tests: T1 T2 T3  57 1/1 fifo_clr_o = 1'b0; Tests: T1 T2 T3  58 1/1 fifo_pop_o = 1'b0; Tests: T1 T2 T3  59 1/1 ack_sm_err_o = 1'b0; Tests: T1 T2 T3  60 1/1 unique case (state_q) Tests: T1 T2 T3  61 Disabled: begin 62 1/1 if (enable_i) begin Tests: T1 T2 T3  63 1/1 state_d = EndPointClear; Tests: T1 T2 T3  64 1/1 fifo_clr_o = 1'b1; Tests: T1 T2 T3  65 end MISSING_ELSE 66 end 67 EndPointClear: begin 68 1/1 state_d = Idle; Tests: T1 T2 T3  69 end 70 Idle: begin 71 1/1 if (req_i) begin Tests: T1 T2 T3  72 1/1 if (fifo_not_empty_i) begin Tests: T9 T41 T18  73 1/1 fifo_pop_o = 1'b1; Tests: T9 T41 T18  74 end MISSING_ELSE 75 1/1 state_d = DataWait; Tests: T9 T41 T18  76 end MISSING_ELSE 77 end 78 DataWait: begin 79 1/1 if (fifo_not_empty_i) begin Tests: T9 T41 T18  80 1/1 state_d = AckPls; Tests: T9 T41 T18  81 end MISSING_ELSE 82 end 83 AckPls: begin 84 1/1 ack_o = 1'b1; Tests: T9 T41 T18  85 1/1 state_d = Idle; Tests: T9 T41 T18  86 end 87 Error: begin 88 1/1 ack_sm_err_o = 1'b1; Tests: T3 T4 T28  89 end 90 default: begin 91 ack_sm_err_o = 1'b1; 92 state_d = Error; 93 end 94 endcase // unique case (state_q) 95 96 // If local escalation is seen, transition directly to 97 // error state. 98 1/1 if (local_escalate_i) begin Tests: T1 T2 T3  99 1/1 state_d = Error; Tests: T3 T4 T28  100 // Tie off outputs, except for ack_sm_err_o. 101 1/1 ack_o = 1'b0; Tests: T3 T4 T28  102 1/1 fifo_clr_o = 1'b0; Tests: T3 T4 T28  103 1/1 fifo_pop_o = 1'b0; Tests: T3 T4 T28  104 1/1 end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin Tests: T1 T2 T3  105 // Only disable if state is legal and not Disabled or Error. 106 // Even when disabled, illegal states must result in a transition to Error. 107 1/1 state_d = Disabled; Tests: T21 T4 T9  108 // Tie off all outputs, except for ack_sm_err_o. 109 1/1 ack_o = 1'b0; Tests: T21 T4 T9  110 1/1 fifo_pop_o = 1'b0; Tests: T21 T4 T9  111 1/1 fifo_clr_o = 1'b0; Tests: T21 T4 T9  112 end MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT21,T4,T9

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 12 85.71
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
AckPls 80 Covered T9,T41,T18
DataWait 75 Covered T9,T41,T18
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T3,T4,T28
Idle 68 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
AckPls->Disabled 107 Not Covered
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T9,T41,T18
DataWait->AckPls 80 Covered T9,T41,T18
DataWait->Disabled 107 Covered T41,T56,T119
DataWait->Error 99 Covered T208
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T15,T16,T17
EndPointClear->Disabled 107 Covered T129,T96,T116
EndPointClear->Error 99 Covered T4,T15,T16
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T9,T41,T18
Idle->Disabled 107 Covered T21,T4,T9
Idle->Error 99 Covered T3,T28,T6



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00


52 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled) -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


60 unique case (state_q) -1- 61 Disabled: begin 62 if (enable_i) begin -2- 63 state_d = EndPointClear; ==> 64 fifo_clr_o = 1'b1; 65 end MISSING_ELSE ==> 66 end 67 EndPointClear: begin 68 state_d = Idle; ==> 69 end 70 Idle: begin 71 if (req_i) begin -3- 72 if (fifo_not_empty_i) begin -4- 73 fifo_pop_o = 1'b1; ==> 74 end MISSING_ELSE ==> 75 state_d = DataWait; 76 end MISSING_ELSE ==> 77 end 78 DataWait: begin 79 if (fifo_not_empty_i) begin -5- 80 state_d = AckPls; ==> 81 end MISSING_ELSE ==> 82 end 83 AckPls: begin 84 ack_o = 1'b1; ==> 85 state_d = Idle; 86 end 87 Error: begin 88 ack_sm_err_o = 1'b1; ==> 89 end 90 default: begin 91 ack_sm_err_o = 1'b1; ==>

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T9,T41,T18
Idle - 1 0 - Covered T9,T41,T18
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T9,T41,T18
DataWait - - - 0 Covered T9,T41,T18
AckPls - - - - Covered T9,T41,T18
Error - - - - Covered T3,T4,T28
default - - - - Covered T15,T16,T17


98 if (local_escalate_i) begin -1- 99 state_d = Error; ==> 100 // Tie off outputs, except for ack_sm_err_o. 101 ack_o = 1'b0; 102 fifo_clr_o = 1'b0; 103 fifo_pop_o = 1'b0; 104 end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin -2- 105 // Only disable if state is legal and not Disabled or Error. 106 // Even when disabled, illegal states must result in a transition to Error. 107 state_d = Disabled; ==> 108 // Tie off all outputs, except for ack_sm_err_o. 109 ack_o = 1'b0; 110 fifo_pop_o = 1'b0; 111 fifo_clr_o = 1'b0; 112 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T3,T4,T28
0 1 Covered T21,T4,T9
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
AckSmErrorStStable_A 9178401 154828 0 0
FpvSecCmErrorStEscalate_A 9178401 155873 0 0
u_state_regs_A 9178401 9000299 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9178401 154828 0 0
T3 865 358 0 0
T4 1780 1070 0 0
T5 7672 0 0 0
T6 0 1178 0 0
T7 0 270 0 0
T8 0 329 0 0
T9 1704 0 0 0
T15 0 10695 0 0
T20 4568 0 0 0
T21 1126 0 0 0
T22 2116 0 0 0
T23 1233 0 0 0
T24 990 0 0 0
T28 0 580 0 0
T43 1566 0 0 0
T68 0 487 0 0
T74 0 1119 0 0
T75 0 280 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9178401 155873 0 0
T3 865 359 0 0
T4 1780 1071 0 0
T5 7672 0 0 0
T6 0 1179 0 0
T7 0 271 0 0
T8 0 330 0 0
T9 1704 0 0 0
T15 0 10825 0 0
T20 4568 0 0 0
T21 1126 0 0 0
T22 2116 0 0 0
T23 1233 0 0 0
T24 990 0 0 0
T28 0 581 0 0
T43 1566 0 0 0
T68 0 488 0 0
T74 0 1120 0 0
T75 0 281 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9178401 9000299 0 0
T1 1173 1087 0 0
T2 1350 1260 0 0
T3 865 688 0 0
T4 1780 1634 0 0
T5 7672 7169 0 0
T9 1704 1627 0 0
T20 4568 4481 0 0
T21 1126 1036 0 0
T22 2116 2018 0 0
T23 1233 1178 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00

51 52 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled) Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled): 52.1 `ifdef SIMULATION 52.2 prim_sparse_fsm_flop #( 52.3 .StateEnumT(state_e), 52.4 .Width($bits(state_e)), 52.5 .ResetValue($bits(state_e)'(Disabled)), 52.6 .EnableAlertTriggerSVA(1), 52.7 .CustomForceName("state_q") 52.8 ) u_state_regs ( 52.9 .clk_i ( clk_i ), 52.10 .rst_ni ( rst_ni ), 52.11 .state_i ( state_d ), 52.12 .state_o ( ) 52.13 ); 52.14 always_ff @(posedge clk_i or negedge rst_ni) begin 52.15 1/1 if (!rst_ni) begin Tests: T1 T2 T3  52.16 1/1 state_q <= Disabled; Tests: T1 T2 T3  52.17 end else begin 52.18 1/1 state_q <= state_d; Tests: T1 T2 T3  52.19 end 52.20 end 52.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o)) 52.22 else begin 52.23 `ifdef UVM 52.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 52.25 "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1); 52.26 `else 52.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__, 52.28 `PRIM_STRINGIFY(u_state_regs_A)); 52.29 `endif 52.30 end 52.31 `else 52.32 prim_sparse_fsm_flop #( 52.33 .StateEnumT(state_e), 52.34 .Width($bits(state_e)), 52.35 .ResetValue($bits(state_e)'(Disabled)), 52.36 .EnableAlertTriggerSVA(1) 52.37 ) u_state_regs ( 52.38 .clk_i ( `PRIM_FLOP_CLK ), 52.39 .rst_ni ( `PRIM_FLOP_RST ), 52.40 .state_i ( state_d ), 52.41 .state_o ( state_q ) 52.42 ); 52.43 `endif53 54 always_comb begin 55 1/1 state_d = state_q; Tests: T1 T2 T3  56 1/1 ack_o = 1'b0; Tests: T1 T2 T3  57 1/1 fifo_clr_o = 1'b0; Tests: T1 T2 T3  58 1/1 fifo_pop_o = 1'b0; Tests: T1 T2 T3  59 1/1 ack_sm_err_o = 1'b0; Tests: T1 T2 T3  60 1/1 unique case (state_q) Tests: T1 T2 T3  61 Disabled: begin 62 1/1 if (enable_i) begin Tests: T1 T2 T3  63 1/1 state_d = EndPointClear; Tests: T1 T2 T3  64 1/1 fifo_clr_o = 1'b1; Tests: T1 T2 T3  65 end MISSING_ELSE 66 end 67 EndPointClear: begin 68 1/1 state_d = Idle; Tests: T1 T2 T3  69 end 70 Idle: begin 71 1/1 if (req_i) begin Tests: T1 T2 T3  72 1/1 if (fifo_not_empty_i) begin Tests: T42 T55 T49  73 1/1 fifo_pop_o = 1'b1; Tests: T42 T55 T49  74 end MISSING_ELSE 75 1/1 state_d = DataWait; Tests: T42 T55 T49  76 end MISSING_ELSE 77 end 78 DataWait: begin 79 1/1 if (fifo_not_empty_i) begin Tests: T42 T55 T49  80 1/1 state_d = AckPls; Tests: T42 T55 T49  81 end MISSING_ELSE 82 end 83 AckPls: begin 84 1/1 ack_o = 1'b1; Tests: T42 T55 T49  85 1/1 state_d = Idle; Tests: T42 T55 T49  86 end 87 Error: begin 88 1/1 ack_sm_err_o = 1'b1; Tests: T3 T4 T28  89 end 90 default: begin 91 ack_sm_err_o = 1'b1; 92 state_d = Error; 93 end 94 endcase // unique case (state_q) 95 96 // If local escalation is seen, transition directly to 97 // error state. 98 1/1 if (local_escalate_i) begin Tests: T1 T2 T3  99 1/1 state_d = Error; Tests: T3 T4 T28  100 // Tie off outputs, except for ack_sm_err_o. 101 1/1 ack_o = 1'b0; Tests: T3 T4 T28  102 1/1 fifo_clr_o = 1'b0; Tests: T3 T4 T28  103 1/1 fifo_pop_o = 1'b0; Tests: T3 T4 T28  104 1/1 end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin Tests: T1 T2 T3  105 // Only disable if state is legal and not Disabled or Error. 106 // Even when disabled, illegal states must result in a transition to Error. 107 1/1 state_d = Disabled; Tests: T21 T4 T9  108 // Tie off all outputs, except for ack_sm_err_o. 109 1/1 ack_o = 1'b0; Tests: T21 T4 T9  110 1/1 fifo_pop_o = 1'b0; Tests: T21 T4 T9  111 1/1 fifo_clr_o = 1'b0; Tests: T21 T4 T9  112 end MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT21,T4,T9

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 12 85.71
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
AckPls 80 Covered T42,T55,T49
DataWait 75 Covered T42,T55,T49
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T3,T4,T28
Idle 68 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
AckPls->Disabled 107 Not Covered
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T42,T55,T49
DataWait->AckPls 80 Covered T42,T55,T49
DataWait->Disabled 107 Covered T104,T231
DataWait->Error 99 Covered T232,T233,T183
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T15,T16,T17
EndPointClear->Disabled 107 Covered T129,T96,T116
EndPointClear->Error 99 Covered T4,T15,T16
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T42,T55,T49
Idle->Disabled 107 Covered T21,T4,T9
Idle->Error 99 Covered T3,T28,T6



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00


52 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled) -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


60 unique case (state_q) -1- 61 Disabled: begin 62 if (enable_i) begin -2- 63 state_d = EndPointClear; ==> 64 fifo_clr_o = 1'b1; 65 end MISSING_ELSE ==> 66 end 67 EndPointClear: begin 68 state_d = Idle; ==> 69 end 70 Idle: begin 71 if (req_i) begin -3- 72 if (fifo_not_empty_i) begin -4- 73 fifo_pop_o = 1'b1; ==> 74 end MISSING_ELSE ==> 75 state_d = DataWait; 76 end MISSING_ELSE ==> 77 end 78 DataWait: begin 79 if (fifo_not_empty_i) begin -5- 80 state_d = AckPls; ==> 81 end MISSING_ELSE ==> 82 end 83 AckPls: begin 84 ack_o = 1'b1; ==> 85 state_d = Idle; 86 end 87 Error: begin 88 ack_sm_err_o = 1'b1; ==> 89 end 90 default: begin 91 ack_sm_err_o = 1'b1; ==>

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T42,T55,T49
Idle - 1 0 - Covered T42,T55,T49
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T42,T55,T49
DataWait - - - 0 Covered T55,T49,T100
AckPls - - - - Covered T42,T55,T49
Error - - - - Covered T3,T4,T28
default - - - - Covered T15,T16,T17


98 if (local_escalate_i) begin -1- 99 state_d = Error; ==> 100 // Tie off outputs, except for ack_sm_err_o. 101 ack_o = 1'b0; 102 fifo_clr_o = 1'b0; 103 fifo_pop_o = 1'b0; 104 end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin -2- 105 // Only disable if state is legal and not Disabled or Error. 106 // Even when disabled, illegal states must result in a transition to Error. 107 state_d = Disabled; ==> 108 // Tie off all outputs, except for ack_sm_err_o. 109 ack_o = 1'b0; 110 fifo_pop_o = 1'b0; 111 fifo_clr_o = 1'b0; 112 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T3,T4,T28
0 1 Covered T21,T4,T9
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
AckSmErrorStStable_A 9178401 154828 0 0
FpvSecCmErrorStEscalate_A 9178401 155873 0 0
u_state_regs_A 9178401 9000299 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9178401 154828 0 0
T3 865 358 0 0
T4 1780 1070 0 0
T5 7672 0 0 0
T6 0 1178 0 0
T7 0 270 0 0
T8 0 329 0 0
T9 1704 0 0 0
T15 0 10695 0 0
T20 4568 0 0 0
T21 1126 0 0 0
T22 2116 0 0 0
T23 1233 0 0 0
T24 990 0 0 0
T28 0 580 0 0
T43 1566 0 0 0
T68 0 487 0 0
T74 0 1119 0 0
T75 0 280 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9178401 155873 0 0
T3 865 359 0 0
T4 1780 1071 0 0
T5 7672 0 0 0
T6 0 1179 0 0
T7 0 271 0 0
T8 0 330 0 0
T9 1704 0 0 0
T15 0 10825 0 0
T20 4568 0 0 0
T21 1126 0 0 0
T22 2116 0 0 0
T23 1233 0 0 0
T24 990 0 0 0
T28 0 581 0 0
T43 1566 0 0 0
T68 0 488 0 0
T74 0 1120 0 0
T75 0 281 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9178401 9000299 0 0
T1 1173 1087 0 0
T2 1350 1260 0 0
T3 865 688 0 0
T4 1780 1634 0 0
T5 7672 7169 0 0
T9 1704 1627 0 0
T20 4568 4481 0 0
T21 1126 1036 0 0
T22 2116 2018 0 0
T23 1233 1178 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00

51 52 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled) Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled): 52.1 `ifdef SIMULATION 52.2 prim_sparse_fsm_flop #( 52.3 .StateEnumT(state_e), 52.4 .Width($bits(state_e)), 52.5 .ResetValue($bits(state_e)'(Disabled)), 52.6 .EnableAlertTriggerSVA(1), 52.7 .CustomForceName("state_q") 52.8 ) u_state_regs ( 52.9 .clk_i ( clk_i ), 52.10 .rst_ni ( rst_ni ), 52.11 .state_i ( state_d ), 52.12 .state_o ( ) 52.13 ); 52.14 always_ff @(posedge clk_i or negedge rst_ni) begin 52.15 1/1 if (!rst_ni) begin Tests: T1 T2 T3  52.16 1/1 state_q <= Disabled; Tests: T1 T2 T3  52.17 end else begin 52.18 1/1 state_q <= state_d; Tests: T1 T2 T3  52.19 end 52.20 end 52.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o)) 52.22 else begin 52.23 `ifdef UVM 52.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 52.25 "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1); 52.26 `else 52.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__, 52.28 `PRIM_STRINGIFY(u_state_regs_A)); 52.29 `endif 52.30 end 52.31 `else 52.32 prim_sparse_fsm_flop #( 52.33 .StateEnumT(state_e), 52.34 .Width($bits(state_e)), 52.35 .ResetValue($bits(state_e)'(Disabled)), 52.36 .EnableAlertTriggerSVA(1) 52.37 ) u_state_regs ( 52.38 .clk_i ( `PRIM_FLOP_CLK ), 52.39 .rst_ni ( `PRIM_FLOP_RST ), 52.40 .state_i ( state_d ), 52.41 .state_o ( state_q ) 52.42 ); 52.43 `endif53 54 always_comb begin 55 1/1 state_d = state_q; Tests: T1 T2 T3  56 1/1 ack_o = 1'b0; Tests: T1 T2 T3  57 1/1 fifo_clr_o = 1'b0; Tests: T1 T2 T3  58 1/1 fifo_pop_o = 1'b0; Tests: T1 T2 T3  59 1/1 ack_sm_err_o = 1'b0; Tests: T1 T2 T3  60 1/1 unique case (state_q) Tests: T1 T2 T3  61 Disabled: begin 62 1/1 if (enable_i) begin Tests: T1 T2 T3  63 1/1 state_d = EndPointClear; Tests: T1 T2 T3  64 1/1 fifo_clr_o = 1'b1; Tests: T1 T2 T3  65 end MISSING_ELSE 66 end 67 EndPointClear: begin 68 1/1 state_d = Idle; Tests: T1 T2 T3  69 end 70 Idle: begin 71 1/1 if (req_i) begin Tests: T1 T2 T3  72 1/1 if (fifo_not_empty_i) begin Tests: T1 T2 T3  73 1/1 fifo_pop_o = 1'b1; Tests: T1 T2 T3  74 end MISSING_ELSE 75 1/1 state_d = DataWait; Tests: T1 T2 T3  76 end MISSING_ELSE 77 end 78 DataWait: begin 79 1/1 if (fifo_not_empty_i) begin Tests: T1 T2 T3  80 1/1 state_d = AckPls; Tests: T1 T2 T3  81 end MISSING_ELSE 82 end 83 AckPls: begin 84 1/1 ack_o = 1'b1; Tests: T1 T2 T3  85 1/1 state_d = Idle; Tests: T1 T2 T3  86 end 87 Error: begin 88 1/1 ack_sm_err_o = 1'b1; Tests: T3 T4 T28  89 end 90 default: begin 91 ack_sm_err_o = 1'b1; 92 state_d = Error; 93 end 94 endcase // unique case (state_q) 95 96 // If local escalation is seen, transition directly to 97 // error state. 98 1/1 if (local_escalate_i) begin Tests: T1 T2 T3  99 1/1 state_d = Error; Tests: T3 T4 T28  100 // Tie off outputs, except for ack_sm_err_o. 101 1/1 ack_o = 1'b0; Tests: T3 T4 T28  102 1/1 fifo_clr_o = 1'b0; Tests: T3 T4 T28  103 1/1 fifo_pop_o = 1'b0; Tests: T3 T4 T28  104 1/1 end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin Tests: T1 T2 T3  105 // Only disable if state is legal and not Disabled or Error. 106 // Even when disabled, illegal states must result in a transition to Error. 107 1/1 state_d = Disabled; Tests: T21 T4 T9  108 // Tie off all outputs, except for ack_sm_err_o. 109 1/1 ack_o = 1'b0; Tests: T21 T4 T9  110 1/1 fifo_pop_o = 1'b0; Tests: T21 T4 T9  111 1/1 fifo_clr_o = 1'b0; Tests: T21 T4 T9  112 end MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT21,T4,T9

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 13 92.86
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
AckPls 80 Covered T1,T2,T3
DataWait 75 Covered T1,T2,T3
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T3,T4,T28
Idle 68 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
AckPls->Disabled 107 Covered T214
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T1,T2,T3
DataWait->AckPls 80 Covered T1,T2,T3
DataWait->Disabled 107 Covered T100,T234,T35
DataWait->Error 99 Covered T6,T68,T7
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T15,T16,T17
EndPointClear->Disabled 107 Covered T129,T96,T116
EndPointClear->Error 99 Covered T4,T15,T16
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T1,T2,T3
Idle->Disabled 107 Covered T21,T4,T9
Idle->Error 99 Covered T15,T74,T8



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00


52 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled) -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


60 unique case (state_q) -1- 61 Disabled: begin 62 if (enable_i) begin -2- 63 state_d = EndPointClear; ==> 64 fifo_clr_o = 1'b1; 65 end MISSING_ELSE ==> 66 end 67 EndPointClear: begin 68 state_d = Idle; ==> 69 end 70 Idle: begin 71 if (req_i) begin -3- 72 if (fifo_not_empty_i) begin -4- 73 fifo_pop_o = 1'b1; ==> 74 end MISSING_ELSE ==> 75 state_d = DataWait; 76 end MISSING_ELSE ==> 77 end 78 DataWait: begin 79 if (fifo_not_empty_i) begin -5- 80 state_d = AckPls; ==> 81 end MISSING_ELSE ==> 82 end 83 AckPls: begin 84 ack_o = 1'b1; ==> 85 state_d = Idle; 86 end 87 Error: begin 88 ack_sm_err_o = 1'b1; ==> 89 end 90 default: begin 91 ack_sm_err_o = 1'b1; ==>

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T1,T2,T3
Idle - 1 0 - Covered T1,T2,T3
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T1,T2,T3
DataWait - - - 0 Covered T1,T2,T20
AckPls - - - - Covered T1,T2,T3
Error - - - - Covered T3,T4,T28
default - - - - Covered T3,T28,T15


98 if (local_escalate_i) begin -1- 99 state_d = Error; ==> 100 // Tie off outputs, except for ack_sm_err_o. 101 ack_o = 1'b0; 102 fifo_clr_o = 1'b0; 103 fifo_pop_o = 1'b0; 104 end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin -2- 105 // Only disable if state is legal and not Disabled or Error. 106 // Even when disabled, illegal states must result in a transition to Error. 107 state_d = Disabled; ==> 108 // Tie off all outputs, except for ack_sm_err_o. 109 ack_o = 1'b0; 110 fifo_pop_o = 1'b0; 111 fifo_clr_o = 1'b0; 112 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T3,T4,T28
0 1 Covered T21,T4,T9
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
AckSmErrorStStable_A 9178401 152678 0 0
FpvSecCmErrorStEscalate_A 9178401 153723 0 0
u_state_regs_A 9137157 8959055 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9178401 152678 0 0
T3 865 308 0 0
T4 1780 1070 0 0
T5 7672 0 0 0
T6 0 1178 0 0
T7 0 270 0 0
T8 0 329 0 0
T9 1704 0 0 0
T15 0 10695 0 0
T20 4568 0 0 0
T21 1126 0 0 0
T22 2116 0 0 0
T23 1233 0 0 0
T24 990 0 0 0
T28 0 530 0 0
T43 1566 0 0 0
T68 0 487 0 0
T74 0 1119 0 0
T75 0 230 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9178401 153723 0 0
T3 865 309 0 0
T4 1780 1071 0 0
T5 7672 0 0 0
T6 0 1179 0 0
T7 0 271 0 0
T8 0 330 0 0
T9 1704 0 0 0
T15 0 10825 0 0
T20 4568 0 0 0
T21 1126 0 0 0
T22 2116 0 0 0
T23 1233 0 0 0
T24 990 0 0 0
T28 0 531 0 0
T43 1566 0 0 0
T68 0 488 0 0
T74 0 1120 0 0
T75 0 231 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9137157 8959055 0 0
T1 1173 1087 0 0
T2 1350 1260 0 0
T3 753 576 0 0
T4 1660 1514 0 0
T5 7672 7169 0 0
T9 1704 1627 0 0
T20 4568 4481 0 0
T21 1126 1036 0 0
T22 2116 2018 0 0
T23 1233 1178 0 0