Line Coverage for Instance : tb.dut.u_reg.u_recov_alert_sts_auto_req_mode_field_alert.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
112 end else if (SwAccess == SwAccessW0C) begin : gen_w0c
113 1/1 assign wr_en = we | de;
Tests: T1 T2 T3
114 if (Mubi) begin : gen_mubi
115 if (DW == 4) begin : gen_mubi4
116 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q),
117 (we ? prim_mubi_pkg::mubi4_t'(wd) :
118 prim_mubi_pkg::MuBi4True));
119 end else if (DW == 8) begin : gen_mubi8
120 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q),
121 (we ? prim_mubi_pkg::mubi8_t'(wd) :
122 prim_mubi_pkg::MuBi8True));
123 end else if (DW == 12) begin : gen_mubi12
124 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q),
125 (we ? prim_mubi_pkg::mubi12_t'(wd) :
126 prim_mubi_pkg::MuBi12True));
127 end else if (DW == 16) begin : gen_mubi16
128 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q),
129 (we ? prim_mubi_pkg::mubi16_t'(wd) :
130 prim_mubi_pkg::MuBi16True));
131 end else begin : gen_invalid_mubi
132 $error("%m: Invalid width for MuBi");
133 end
134 end else begin : gen_non_mubi
135 1/1 assign wr_data = (de ? d : q) & (we ? wd : '1);
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_recov_alert_sts_auto_req_mode_field_alert.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 10 | 10 | 100.00 |
| Logical | 10 | 10 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T26,T42,T121 |
| 1 | 0 | Covered | T22,T14,T26 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T42,T121 |
| 1 | 1 | Covered | T26,T42,T121 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T42,T121 |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T22,T14,T26 |
Line Coverage for Instance : tb.dut.u_reg.u_recov_alert_sts_cmd_fifo_rst_field_alert.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
112 end else if (SwAccess == SwAccessW0C) begin : gen_w0c
113 1/1 assign wr_en = we | de;
Tests: T1 T2 T3
114 if (Mubi) begin : gen_mubi
115 if (DW == 4) begin : gen_mubi4
116 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q),
117 (we ? prim_mubi_pkg::mubi4_t'(wd) :
118 prim_mubi_pkg::MuBi4True));
119 end else if (DW == 8) begin : gen_mubi8
120 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q),
121 (we ? prim_mubi_pkg::mubi8_t'(wd) :
122 prim_mubi_pkg::MuBi8True));
123 end else if (DW == 12) begin : gen_mubi12
124 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q),
125 (we ? prim_mubi_pkg::mubi12_t'(wd) :
126 prim_mubi_pkg::MuBi12True));
127 end else if (DW == 16) begin : gen_mubi16
128 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q),
129 (we ? prim_mubi_pkg::mubi16_t'(wd) :
130 prim_mubi_pkg::MuBi16True));
131 end else begin : gen_invalid_mubi
132 $error("%m: Invalid width for MuBi");
133 end
134 end else begin : gen_non_mubi
135 1/1 assign wr_data = (de ? d : q) & (we ? wd : '1);
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_recov_alert_sts_cmd_fifo_rst_field_alert.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 10 | 10 | 100.00 |
| Logical | 10 | 10 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T135,T58,T139 |
| 1 | 0 | Covered | T22,T14,T26 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T135,T58,T139 |
| 1 | 1 | Covered | T135,T58,T139 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T135,T58,T139 |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T22,T14,T26 |
Line Coverage for Instance : tb.dut.u_reg.u_recov_alert_sts_edn_bus_cmp_alert.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
112 end else if (SwAccess == SwAccessW0C) begin : gen_w0c
113 1/1 assign wr_en = we | de;
Tests: T20 T22 T14
114 if (Mubi) begin : gen_mubi
115 if (DW == 4) begin : gen_mubi4
116 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q),
117 (we ? prim_mubi_pkg::mubi4_t'(wd) :
118 prim_mubi_pkg::MuBi4True));
119 end else if (DW == 8) begin : gen_mubi8
120 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q),
121 (we ? prim_mubi_pkg::mubi8_t'(wd) :
122 prim_mubi_pkg::MuBi8True));
123 end else if (DW == 12) begin : gen_mubi12
124 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q),
125 (we ? prim_mubi_pkg::mubi12_t'(wd) :
126 prim_mubi_pkg::MuBi12True));
127 end else if (DW == 16) begin : gen_mubi16
128 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q),
129 (we ? prim_mubi_pkg::mubi16_t'(wd) :
130 prim_mubi_pkg::MuBi16True));
131 end else begin : gen_invalid_mubi
132 $error("%m: Invalid width for MuBi");
133 end
134 end else begin : gen_non_mubi
135 1/1 assign wr_data = (de ? d : q) & (we ? wd : '1);
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_recov_alert_sts_edn_bus_cmp_alert.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 10 | 10 | 100.00 |
| Logical | 10 | 10 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T22,T14,T26 |
| 1 | 0 | Covered | T22,T14,T26 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T22,T14,T26 |
| 1 | 1 | Covered | T22,T14,T26 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T22,T14,T26 |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T22,T14,T26 |
Line Coverage for Instance : tb.dut.u_reg.u_recov_alert_sts_csrng_ack_err.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
112 end else if (SwAccess == SwAccessW0C) begin : gen_w0c
113 1/1 assign wr_en = we | de;
Tests: T22 T14 T26
114 if (Mubi) begin : gen_mubi
115 if (DW == 4) begin : gen_mubi4
116 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q),
117 (we ? prim_mubi_pkg::mubi4_t'(wd) :
118 prim_mubi_pkg::MuBi4True));
119 end else if (DW == 8) begin : gen_mubi8
120 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q),
121 (we ? prim_mubi_pkg::mubi8_t'(wd) :
122 prim_mubi_pkg::MuBi8True));
123 end else if (DW == 12) begin : gen_mubi12
124 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q),
125 (we ? prim_mubi_pkg::mubi12_t'(wd) :
126 prim_mubi_pkg::MuBi12True));
127 end else if (DW == 16) begin : gen_mubi16
128 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q),
129 (we ? prim_mubi_pkg::mubi16_t'(wd) :
130 prim_mubi_pkg::MuBi16True));
131 end else begin : gen_invalid_mubi
132 $error("%m: Invalid width for MuBi");
133 end
134 end else begin : gen_non_mubi
135 1/1 assign wr_data = (de ? d : q) & (we ? wd : '1);
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_recov_alert_sts_csrng_ack_err.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 10 | 10 | 100.00 |
| Logical | 10 | 10 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T22,T14,T26 |
| 1 | 0 | Covered | T22,T14,T26 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T22,T14,T26 |
| 1 | 1 | Covered | T22,T14,T26 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T22,T14,T26 |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T22,T14,T26 |
Line Coverage for Instance : tb.dut.u_reg.u_err_code_sfifo_rescmd_err.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 1 | 50.00 |
| CONT_ASSIGN | 43 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 51 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| CONT_ASSIGN | 53 | 0 | 0 | |
42 end else if (SwAccess == SwAccessRO) begin : gen_ro
43 1/1 assign wr_en = de;
Tests: T1 T2 T3
44 0/1 ==> assign wr_data = d;
45 // Unused we, wd, q - Prevent lint errors.
46 logic unused_we;
47 logic [DW-1:0] unused_wd;
48 logic [DW-1:0] unused_q;
49 //VCS coverage off
50 // pragma coverage off
51 unreachable assign unused_we = we;
52 unreachable assign unused_wd = wd;
53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.u_reg.u_err_code_sfifo_gencmd_err.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 1 | 50.00 |
| CONT_ASSIGN | 43 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 51 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| CONT_ASSIGN | 53 | 0 | 0 | |
42 end else if (SwAccess == SwAccessRO) begin : gen_ro
43 1/1 assign wr_en = de;
Tests: T1 T2 T3
44 0/1 ==> assign wr_data = d;
45 // Unused we, wd, q - Prevent lint errors.
46 logic unused_we;
47 logic [DW-1:0] unused_wd;
48 logic [DW-1:0] unused_q;
49 //VCS coverage off
50 // pragma coverage off
51 unreachable assign unused_we = we;
52 unreachable assign unused_wd = wd;
53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.u_reg.u_err_code_edn_ack_sm_err.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 1 | 50.00 |
| CONT_ASSIGN | 43 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 51 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| CONT_ASSIGN | 53 | 0 | 0 | |
42 end else if (SwAccess == SwAccessRO) begin : gen_ro
43 1/1 assign wr_en = de;
Tests: T1 T2 T3
44 0/1 ==> assign wr_data = d;
45 // Unused we, wd, q - Prevent lint errors.
46 logic unused_we;
47 logic [DW-1:0] unused_wd;
48 logic [DW-1:0] unused_q;
49 //VCS coverage off
50 // pragma coverage off
51 unreachable assign unused_we = we;
52 unreachable assign unused_wd = wd;
53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.u_reg.u_err_code_edn_main_sm_err.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 1 | 50.00 |
| CONT_ASSIGN | 43 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 51 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| CONT_ASSIGN | 53 | 0 | 0 | |
42 end else if (SwAccess == SwAccessRO) begin : gen_ro
43 1/1 assign wr_en = de;
Tests: T1 T2 T3
44 0/1 ==> assign wr_data = d;
45 // Unused we, wd, q - Prevent lint errors.
46 logic unused_we;
47 logic [DW-1:0] unused_wd;
48 logic [DW-1:0] unused_q;
49 //VCS coverage off
50 // pragma coverage off
51 unreachable assign unused_we = we;
52 unreachable assign unused_wd = wd;
53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.u_reg.u_err_code_edn_cntr_err.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 1 | 50.00 |
| CONT_ASSIGN | 43 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 51 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| CONT_ASSIGN | 53 | 0 | 0 | |
42 end else if (SwAccess == SwAccessRO) begin : gen_ro
43 1/1 assign wr_en = de;
Tests: T1 T2 T3
44 0/1 ==> assign wr_data = d;
45 // Unused we, wd, q - Prevent lint errors.
46 logic unused_we;
47 logic [DW-1:0] unused_wd;
48 logic [DW-1:0] unused_q;
49 //VCS coverage off
50 // pragma coverage off
51 unreachable assign unused_we = we;
52 unreachable assign unused_wd = wd;
53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.u_reg.u_err_code_fifo_write_err.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 1 | 50.00 |
| CONT_ASSIGN | 43 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 51 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| CONT_ASSIGN | 53 | 0 | 0 | |
42 end else if (SwAccess == SwAccessRO) begin : gen_ro
43 1/1 assign wr_en = de;
Tests: T1 T2 T3
44 0/1 ==> assign wr_data = d;
45 // Unused we, wd, q - Prevent lint errors.
46 logic unused_we;
47 logic [DW-1:0] unused_wd;
48 logic [DW-1:0] unused_q;
49 //VCS coverage off
50 // pragma coverage off
51 unreachable assign unused_we = we;
52 unreachable assign unused_wd = wd;
53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.u_reg.u_err_code_fifo_read_err.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 1 | 50.00 |
| CONT_ASSIGN | 43 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 51 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| CONT_ASSIGN | 53 | 0 | 0 | |
42 end else if (SwAccess == SwAccessRO) begin : gen_ro
43 1/1 assign wr_en = de;
Tests: T1 T2 T3
44 0/1 ==> assign wr_data = d;
45 // Unused we, wd, q - Prevent lint errors.
46 logic unused_we;
47 logic [DW-1:0] unused_wd;
48 logic [DW-1:0] unused_q;
49 //VCS coverage off
50 // pragma coverage off
51 unreachable assign unused_we = we;
52 unreachable assign unused_wd = wd;
53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.u_reg.u_err_code_fifo_state_err.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 1 | 50.00 |
| CONT_ASSIGN | 43 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 51 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| CONT_ASSIGN | 53 | 0 | 0 | |
42 end else if (SwAccess == SwAccessRO) begin : gen_ro
43 1/1 assign wr_en = de;
Tests: T1 T2 T3
44 0/1 ==> assign wr_data = d;
45 // Unused we, wd, q - Prevent lint errors.
46 logic unused_we;
47 logic [DW-1:0] unused_wd;
48 logic [DW-1:0] unused_q;
49 //VCS coverage off
50 // pragma coverage off
51 unreachable assign unused_we = we;
52 unreachable assign unused_wd = wd;
53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.u_reg.u_err_code_test.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T20 T9 T5
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T1 T2 T3
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_err_code_test.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T20,T9,T5 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T20,T9,T5 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T20,T9,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_err_code_test.wr_en_data_arb
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T20,T9,T5 |
| 0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_main_sm_state.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 1 | 50.00 |
| CONT_ASSIGN | 43 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 51 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| CONT_ASSIGN | 53 | 0 | 0 | |
42 end else if (SwAccess == SwAccessRO) begin : gen_ro
43 0/1 ==> assign wr_en = de;
44 1/1 assign wr_data = d;
Tests: T1 T2 T3
45 // Unused we, wd, q - Prevent lint errors.
46 logic unused_we;
47 logic [DW-1:0] unused_wd;
48 logic [DW-1:0] unused_q;
49 //VCS coverage off
50 // pragma coverage off
51 unreachable assign unused_we = we;
52 unreachable assign unused_wd = wd;
53 unreachable assign unused_q = q;