Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_error_cg

Group : tb.dut.u_edn_cov_if::edn_error_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
75.00	75.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_error_cg	75.00	1	100	1	64	64

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Group Instance : edn_error_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
75.00	1	100	1	64	64

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Summary for Group Instance edn_error_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	2	6	75.00

Variables for Group Instance edn_error_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error_test	8	2	6	75.00	100	1	1	0

Summary for Variable cp_error_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	2	6	75.00

Automatically Generated Bins for cp_error_test

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[EdnFifoWriteErrTest]	0	1	1
auto[EdnFifoReadErrTest]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[EdnSfifoRescmdErrTest]	26	1			T15	5		T16	3		T18	6
auto[EdnSfifoGencmdErrTest]	33	1			T15	5		T16	7		T18	7
auto[EdnAckSmErrTest]	1140	1			T5	1		T17	1		T15	130
auto[EdnMainSmErrTest]	1140	1			T5	1		T17	1		T15	130
auto[EdnCntrErrTest]	111	1			T15	10		T16	10		T7	1
auto[EdnFifoStateErrTest]	59	1			T15	10		T16	10		T18	13