Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	0	21	100.00

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	0	21	100.00	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	145	1			T24	1		T26	1		T38	1
auto_req_mode	143	1			T9	1		T14	1		T11	1
sw_mode	2154	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

294

1

T24

1

T9

1

T26

1

single

96

1

T3

1

T14

1

T51

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1094	1			T1	1		T3	1		T24	1
auto[2]	19	1			T257	1		T41	1		T324	5
auto[3]	88	1			T115	3		T77	1		T79	1
auto[4]	81	1			T92	1		T325	1		T250	70
auto[5]	148	1			T39	1		T61	11		T321	1
auto[6]	153	1			T124	6		T326	5		T12	1
auto[7]	859	1			T2	1		T6	6		T26	1

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	0	21	100.00

Automatically Generated Cross Bins for cr_num_endpoints_mode

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	87	1			T24	1		T38	1		T46	1
auto[1]	auto_req_mode	87	1			T9	1		T14	1		T11	1
auto[1]	sw_mode	920	1			T1	1		T3	1		T71	1
auto[2]	boot_req_mode	3	1			T327	1		T328	1		T329	1
auto[2]	auto_req_mode	6	1			T41	1		T330	1		T331	1
auto[2]	sw_mode	10	1			T257	1		T324	5		T332	1
auto[3]	boot_req_mode	6	1			T333	1		T334	1		T335	1
auto[3]	auto_req_mode	7	1			T77	1		T79	1		T336	1
auto[3]	sw_mode	75	1			T115	3		T337	14		T338	10
auto[4]	boot_req_mode	7	1			T325	1		T339	1		T340	1
auto[4]	auto_req_mode	1	1			T341	1		-	-		-	-
auto[4]	sw_mode	73	1			T92	1		T250	70		T342	1
auto[5]	boot_req_mode	4	1			T343	1		T266	1		T344	1
auto[5]	auto_req_mode	4	1			T345	1		T346	1		T347	1
auto[5]	sw_mode	140	1			T39	1		T61	11		T321	1
auto[6]	boot_req_mode	3	1			T348	1		T349	1		T350	1
auto[6]	auto_req_mode	6	1			T12	1		T351	1		T352	1
auto[6]	sw_mode	144	1			T124	6		T326	5		T353	13
auto[7]	boot_req_mode	35	1			T26	1		T42	1		T354	1
auto[7]	auto_req_mode	32	1			T49	1		T78	1		T101	1
auto[7]	sw_mode	792	1			T2	1		T6	6		T127	5