Group : tb.dut.u_edn_cov_if::edn_cfg_cg
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Group : tb.dut.u_edn_cov_if::edn_cfg_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
edn_cfg_cg 100.00 1 100 1 64 64



Group Instance : edn_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance edn_cfg_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 12 0 12 100.00
Crosses 21 0 21 100.00


Variables for Group Instance edn_cfg_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_mode 3 0 3 100.00 100 1 1 0
cp_num_boot_reqs 2 0 2 100.00 100 1 1 0
cp_num_endpoints 7 0 7 100.00 100 1 1 8


Crosses for Group Instance edn_cfg_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_num_endpoints_mode 21 0 21 100.00 100 1 1 0


Summary for Variable cp_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_mode

Excluded/Illegal bins
NAMECOUNTSTATUS
both 0 Illegal


Covered bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
boot_req_mode 130 1 T3 1 T24 1 T30 1
auto_req_mode 142 1 T10 1 T14 1 T15 1
sw_mode 2846 1 T1 1 T2 1 T4 3


Summary for Variable cp_num_boot_reqs

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins
NAMECOUNTSTATUS
zero 0 Excluded


Covered bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
multiple 297 1 T3 1 T10 1 T30 1
single 103 1 T24 1 T48 1 T77 1


Summary for Variable cp_num_endpoints

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 7 0 7 100.00


Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins
NAME   COUNT   STATUS   
zero 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[1] 881 1 T1 1 T2 1 T4 3
auto[2] 96 1 T57 6 T37 18 T332 1
auto[3] 61 1 T20 1 T78 1 T310 18
auto[4] 240 1 T30 1 T40 1 T307 5
auto[5] 168 1 T72 1 T41 1 T74 1
auto[6] 41 1 T38 26 T333 1 T334 1
auto[7] 1631 1 T3 1 T116 1 T49 1


Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 21 0 21 100.00


Automatically Generated Cross Bins for cr_num_endpoints_mode

Excluded/Illegal bins
cp_num_endpointscp_modeCOUNTSTATUS
[auto[0]] [boot_req_mode , auto_req_mode , sw_mode] -- Excluded (3 bins)


Covered bins
cp_num_endpoints   cp_mode   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[1] boot_req_mode 84 1 T24 1 T63 1 T45 1
auto[1] auto_req_mode 80 1 T10 1 T14 1 T15 1
auto[1] sw_mode 717 1 T1 1 T2 1 T4 3
auto[2] boot_req_mode 4 1 T335 1 T336 1 T337 1
auto[2] auto_req_mode 3 1 T332 1 T338 1 T339 1
auto[2] sw_mode 89 1 T57 6 T37 18 T340 60
auto[3] boot_req_mode 7 1 T341 1 T342 1 T343 1
auto[3] auto_req_mode 5 1 T20 1 T344 1 T345 1
auto[3] sw_mode 49 1 T78 1 T310 18 T346 13
auto[4] boot_req_mode 1 1 T30 1 - - - -
auto[4] auto_req_mode 3 1 T347 1 T348 1 T349 1
auto[4] sw_mode 236 1 T40 1 T307 5 T314 1
auto[5] boot_req_mode 3 1 T72 1 T350 1 T351 1
auto[5] auto_req_mode 7 1 T74 1 T352 1 T353 1
auto[5] sw_mode 158 1 T41 1 T253 4 T354 70
auto[6] boot_req_mode 7 1 T333 1 T355 1 T356 1
auto[6] auto_req_mode 4 1 T334 1 T315 1 T357 1
auto[6] sw_mode 30 1 T38 26 T358 1 T359 1
auto[7] boot_req_mode 24 1 T3 1 T49 1 T76 1
auto[7] auto_req_mode 40 1 T50 1 T93 1 T79 1
auto[7] sw_mode 1567 1 T116 1 T119 15 T311 8