Group : tb.dut.u_edn_cov_if::edn_endpoint_err_req_cg
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Group : tb.dut.u_edn_cov_if::edn_endpoint_err_req_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
edn_endpoint_err_req_cg 100.00 1 100 1 64 64




Group Instance : edn_endpoint_err_req_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance edn_endpoint_err_req_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 7 0 7 100.00


Variables for Group Instance edn_endpoint_err_req_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
endpoint_cg 7 0 7 100.00 100 1 1 0


Summary for Variable endpoint_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 7 0 7 100.00


User Defined Bins for endpoint_cg

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
range[0x0] 377 1 T16 124 T17 58 T18 56
range[0x1] 416 1 T16 124 T17 67 T18 65
range[0x2] 397 1 T16 125 T17 64 T18 68
range[0x3] 380 1 T16 135 T17 59 T18 53
range[0x4] 408 1 T16 136 T17 68 T18 63
range[0x5] 398 1 T16 129 T17 73 T18 76
range[0x6] 398 1 T16 142 T17 64 T18 64