Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	663200	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5260828

1

T1

6

T2

9

T3

22

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1573538	1			T1	41		T2	14		T3	75
values[0x0]	2010957	1			T1	3		T2	7		T3	12
values[0x1]	2339533	1			T1	4		T2	3		T3	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	329598	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5594430

1

T1

19

T2

13

T3

45

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	24015	1			T31	1		T28	1		T7	1
valid_sources[0x01]	21595	1			T4	3		T7	1		T17	1
valid_sources[0x02]	23579	1			T2	1		T67	3		T89	1
valid_sources[0x03]	23036	1			T64	1		T19	1		T18	1
valid_sources[0x04]	22586	1			T3	1		T4	3		T17	22
valid_sources[0x05]	22418	1			T1	16		T3	1		T10	1
valid_sources[0x06]	23219	1			T3	1		T57	3		T66	1
valid_sources[0x07]	22742	1			T4	6		T26	1		T17	1
valid_sources[0x08]	23273	1			T3	2		T4	1		T10	1
valid_sources[0x09]	24254	1			T1	1		T4	4		T40	3
valid_sources[0x0a]	23868	1			T7	1		T57	5		T45	5
valid_sources[0x0b]	22583	1			T3	2		T4	7		T89	1
valid_sources[0x0c]	22935	1			T2	1		T25	2		T64	6
valid_sources[0x0d]	24833	1			T3	1		T67	1		T31	3
valid_sources[0x0e]	23572	1			T10	1		T57	4		T89	1
valid_sources[0x0f]	22588	1			T67	3		T57	1		T40	2
valid_sources[0x10]	24517	1			T4	1		T10	1		T19	1
valid_sources[0x11]	24117	1			T4	6		T5	2		T31	8
valid_sources[0x12]	21288	1			T3	2		T10	2		T57	15
valid_sources[0x13]	23366	1			T4	1		T10	1		T7	1
valid_sources[0x14]	23570	1			T3	1		T4	1		T28	3
valid_sources[0x15]	24109	1			T67	3		T7	1		T19	2
valid_sources[0x16]	23148	1			T4	5		T65	1		T57	10
valid_sources[0x17]	22814	1			T3	1		T57	1		T19	1
valid_sources[0x18]	21397	1			T10	1		T28	1		T19	1
valid_sources[0x19]	26249	1			T7	1		T17	2		T69	1
valid_sources[0x1a]	22470	1			T3	1		T4	1		T28	1
valid_sources[0x1b]	22818	1			T4	1		T88	1		T209	1
valid_sources[0x1c]	23393	1			T1	5		T3	2		T4	2
valid_sources[0x1d]	21983	1			T4	1		T10	1		T57	2
valid_sources[0x1e]	23057	1			T4	1		T10	1		T28	1
valid_sources[0x1f]	22244	1			T89	2		T117	1		T23	1
valid_sources[0x20]	23417	1			T57	3		T89	1		T361	2
valid_sources[0x21]	22150	1			T3	2		T4	3		T25	1
valid_sources[0x22]	24156	1			T3	1		T4	4		T31	2
valid_sources[0x23]	23729	1			T4	7		T67	1		T28	1
valid_sources[0x24]	21695	1			T3	1		T7	1		T17	11
valid_sources[0x25]	24854	1			T10	2		T40	4		T23	3
valid_sources[0x26]	23399	1			T4	1		T26	3		T28	1
valid_sources[0x27]	22805	1			T4	1		T89	1		T115	1
valid_sources[0x28]	21988	1			T4	6		T67	1		T7	1
valid_sources[0x29]	21668	1			T4	2		T10	1		T18	1
valid_sources[0x2a]	22825	1			T4	3		T17	11		T19	1
valid_sources[0x2b]	23366	1			T4	2		T28	1		T17	2
valid_sources[0x2c]	21434	1			T4	1		T28	1		T64	1
valid_sources[0x2d]	23355	1			T10	2		T66	1		T89	1
valid_sources[0x2e]	25863	1			T4	2		T19	1		T66	1
valid_sources[0x2f]	25094	1			T4	3		T5	1		T28	1
valid_sources[0x30]	21999	1			T7	1		T57	2		T40	4
valid_sources[0x31]	23451	1			T4	2		T10	1		T57	4
valid_sources[0x32]	21784	1			T2	1		T28	1		T57	2
valid_sources[0x33]	22973	1			T5	1		T10	1		T89	2
valid_sources[0x34]	22971	1			T5	1		T10	3		T25	1
valid_sources[0x35]	24882	1			T3	2		T5	1		T28	1
valid_sources[0x36]	21885	1			T3	2		T5	1		T57	4
valid_sources[0x37]	23167	1			T9	54		T28	1		T40	1
valid_sources[0x38]	23760	1			T4	4		T7	1		T19	1
valid_sources[0x39]	22764	1			T10	2		T67	2		T28	1
valid_sources[0x3a]	20757	1			T3	1		T26	1		T17	7
valid_sources[0x3b]	25361	1			T3	3		T17	4		T18	6
valid_sources[0x3c]	21762	1			T2	1		T10	5		T28	1
valid_sources[0x3d]	21665	1			T3	2		T4	1		T40	1
valid_sources[0x3e]	23095	1			T3	1		T4	5		T6	16
valid_sources[0x3f]	23644	1			T4	3		T10	2		T17	2
valid_sources[0x40]	22627	1			T4	3		T87	2		T18	2
valid_sources[0x41]	21651	1			T28	1		T89	3		T40	3
valid_sources[0x42]	22943	1			T4	1		T55	6		T23	1
valid_sources[0x43]	24077	1			T4	2		T57	4		T23	2
valid_sources[0x44]	23377	1			T4	1		T7	3		T57	5
valid_sources[0x45]	23181	1			T3	1		T4	2		T67	4
valid_sources[0x46]	22910	1			T10	1		T7	1		T69	1
valid_sources[0x47]	23319	1			T3	1		T4	5		T10	3
valid_sources[0x48]	23505	1			T4	2		T25	2		T28	1
valid_sources[0x49]	22431	1			T4	3		T10	1		T26	1
valid_sources[0x4a]	22979	1			T1	3		T3	1		T4	1
valid_sources[0x4b]	23214	1			T4	3		T57	11		T19	2
valid_sources[0x4c]	23780	1			T4	1		T17	3		T40	2
valid_sources[0x4d]	23009	1			T67	2		T28	1		T7	1
valid_sources[0x4e]	22600	1			T2	1		T4	3		T10	1
valid_sources[0x4f]	22846	1			T2	1		T4	1		T5	1
valid_sources[0x50]	22845	1			T7	1		T57	10		T29	5
valid_sources[0x51]	23990	1			T2	1		T57	7		T40	3
valid_sources[0x52]	21656	1			T10	1		T65	2		T40	1
valid_sources[0x53]	23683	1			T3	3		T4	2		T26	2
valid_sources[0x54]	22616	1			T4	1		T67	2		T28	1
valid_sources[0x55]	23269	1			T4	2		T57	9		T19	1
valid_sources[0x56]	22437	1			T2	1		T4	2		T10	1
valid_sources[0x57]	22124	1			T3	1		T6	29		T24	5
valid_sources[0x58]	24464	1			T10	1		T67	2		T64	2
valid_sources[0x59]	22815	1			T65	1		T17	4		T89	1
valid_sources[0x5a]	23217	1			T7	1		T57	16		T88	1
valid_sources[0x5b]	22451	1			T3	3		T10	1		T7	1
valid_sources[0x5c]	21647	1			T10	1		T26	1		T28	1
valid_sources[0x5d]	22807	1			T4	3		T5	1		T28	1
valid_sources[0x5e]	22309	1			T3	1		T88	1		T89	1
valid_sources[0x5f]	23641	1			T63	1		T17	20		T66	1
valid_sources[0x60]	22342	1			T10	1		T25	1		T28	1
valid_sources[0x61]	23923	1			T4	3		T19	2		T40	1
valid_sources[0x62]	22358	1			T10	4		T57	3		T23	2
valid_sources[0x63]	23383	1			T4	3		T57	13		T89	1
valid_sources[0x64]	23055	1			T57	4		T87	1		T18	4
valid_sources[0x65]	22732	1			T4	1		T10	2		T7	1
valid_sources[0x66]	23368	1			T10	1		T57	2		T29	38
valid_sources[0x67]	25338	1			T10	1		T65	1		T40	1
valid_sources[0x68]	23641	1			T4	4		T7	1		T57	4
valid_sources[0x69]	23740	1			T4	1		T67	1		T14	106
valid_sources[0x6a]	22594	1			T17	1		T57	3		T88	2
valid_sources[0x6b]	23847	1			T4	8		T6	21		T31	6
valid_sources[0x6c]	22016	1			T7	1		T65	1		T57	8
valid_sources[0x6d]	23799	1			T3	3		T4	1		T10	1
valid_sources[0x6e]	23556	1			T4	6		T28	1		T17	12
valid_sources[0x6f]	22004	1			T2	1		T5	1		T31	1
valid_sources[0x70]	24150	1			T4	2		T28	2		T17	5
valid_sources[0x71]	22495	1			T3	1		T69	1		T18	7
valid_sources[0x72]	23914	1			T2	1		T7	1		T17	5
valid_sources[0x73]	23516	1			T3	1		T4	1		T31	3
valid_sources[0x74]	23147	1			T3	1		T89	1		T209	1
valid_sources[0x75]	22894	1			T5	1		T10	1		T7	1
valid_sources[0x76]	22678	1			T4	1		T10	1		T31	4
valid_sources[0x77]	23625	1			T4	1		T17	3		T57	5
valid_sources[0x78]	22371	1			T2	1		T9	1		T28	1
valid_sources[0x79]	24011	1			T2	1		T3	1		T4	5
valid_sources[0x7a]	21359	1			T7	2		T66	1		T88	2
valid_sources[0x7b]	23311	1			T26	2		T69	1		T89	2
valid_sources[0x7c]	23040	1			T10	2		T18	7		T89	1
valid_sources[0x7d]	23788	1			T4	4		T5	1		T28	1
valid_sources[0x7e]	23634	1			T1	1		T3	1		T4	2
valid_sources[0x7f]	22658	1			T10	1		T25	1		T67	3
valid_sources[0x80]	24097	1			T4	5		T31	1		T19	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1324717

1

T1

3

T2

3

T3

4

values[0x0]

all_enables

biggest_size

1968983

1

T1

1

T2

5

T3

10

values[0x1]

all_enables

biggest_size

1967128

1

T1

2

T2

1

T3

8