Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	155349	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

298778

1

T1

9

T2

12

T3

25

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	199145	1			T1	53		T2	20		T3	108
values[0x0]	120468	1			T1	2		T2	3		T3	11
values[0x1]	134514	1			T1	5		T2	7		T3	15

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	104345	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

349782

1

T1

21

T2

17

T3

61

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1622	1			T3	1		T6	1		T9	4
valid_sources[0x01]	1861	1			T1	2		T3	2		T10	5
valid_sources[0x02]	1815	1			T15	8		T68	2		T72	1
valid_sources[0x03]	1876	1			T3	1		T9	1		T59	1
valid_sources[0x04]	2423	1			T22	1		T6	2		T71	1
valid_sources[0x05]	1374	1			T1	2		T3	1		T10	2
valid_sources[0x06]	1477	1			T1	1		T6	2		T15	4
valid_sources[0x07]	1416	1			T6	1		T16	3		T123	3
valid_sources[0x08]	1770	1			T3	1		T23	3		T6	1
valid_sources[0x09]	1562	1			T6	2		T15	6		T16	3
valid_sources[0x0a]	1898	1			T6	2		T72	1		T27	1
valid_sources[0x0b]	1756	1			T60	2		T69	1		T16	4
valid_sources[0x0c]	2199	1			T15	3		T16	1		T123	6
valid_sources[0x0d]	1684	1			T6	2		T71	1		T25	1
valid_sources[0x0e]	1597	1			T3	7		T9	1		T68	1
valid_sources[0x0f]	1362	1			T4	7		T25	1		T16	2
valid_sources[0x10]	1706	1			T6	2		T17	3		T39	1
valid_sources[0x11]	1598	1			T1	1		T6	3		T59	2
valid_sources[0x12]	1874	1			T3	1		T29	7		T16	4
valid_sources[0x13]	3059	1			T6	4		T60	2		T15	7
valid_sources[0x14]	1688	1			T1	3		T9	1		T71	1
valid_sources[0x15]	1457	1			T6	6		T60	2		T10	1
valid_sources[0x16]	1350	1			T3	1		T60	1		T16	4
valid_sources[0x17]	1624	1			T3	1		T71	1		T16	2
valid_sources[0x18]	1580	1			T71	1		T25	1		T27	1
valid_sources[0x19]	1536	1			T3	1		T6	4		T10	1
valid_sources[0x1a]	1437	1			T6	5		T10	2		T27	1
valid_sources[0x1b]	1710	1			T16	1		T123	1		T21	1
valid_sources[0x1c]	1770	1			T9	1		T60	1		T17	6
valid_sources[0x1d]	1661	1			T3	1		T16	2		T21	3
valid_sources[0x1e]	1850	1			T1	5		T10	1		T16	2
valid_sources[0x1f]	1292	1			T3	2		T22	1		T6	4
valid_sources[0x20]	2328	1			T6	1		T16	2		T93	1
valid_sources[0x21]	1383	1			T23	3		T6	1		T10	2
valid_sources[0x22]	1484	1			T16	3		T123	3		T43	1
valid_sources[0x23]	1483	1			T3	1		T16	3		T123	2
valid_sources[0x24]	1508	1			T6	7		T60	1		T28	1
valid_sources[0x25]	1800	1			T3	4		T6	5		T60	1
valid_sources[0x26]	1821	1			T6	3		T25	1		T15	8
valid_sources[0x27]	1509	1			T3	3		T6	3		T9	2
valid_sources[0x28]	1690	1			T10	1		T16	4		T39	1
valid_sources[0x29]	1783	1			T6	2		T16	2		T54	1
valid_sources[0x2a]	2074	1			T3	2		T16	1		T123	1
valid_sources[0x2b]	1526	1			T6	2		T9	2		T60	4
valid_sources[0x2c]	1413	1			T1	4		T3	1		T6	3
valid_sources[0x2d]	1646	1			T6	3		T60	1		T93	2
valid_sources[0x2e]	1447	1			T6	1		T28	1		T16	1
valid_sources[0x2f]	3003	1			T15	14		T93	2		T39	1
valid_sources[0x30]	1566	1			T3	2		T59	2		T15	2
valid_sources[0x31]	1558	1			T60	1		T10	1		T16	6
valid_sources[0x32]	1484	1			T6	2		T71	1		T10	3
valid_sources[0x33]	2482	1			T6	1		T60	2		T15	4
valid_sources[0x34]	1509	1			T6	1		T60	1		T16	1
valid_sources[0x35]	1474	1			T6	6		T59	1		T27	1
valid_sources[0x36]	1736	1			T22	1		T6	2		T10	6
valid_sources[0x37]	2187	1			T60	1		T15	5		T16	4
valid_sources[0x38]	1976	1			T6	2		T25	1		T10	1
valid_sources[0x39]	1676	1			T6	9		T60	1		T16	10
valid_sources[0x3a]	1755	1			T3	1		T6	7		T60	1
valid_sources[0x3b]	2041	1			T3	1		T10	1		T69	1
valid_sources[0x3c]	1619	1			T6	1		T28	2		T15	6
valid_sources[0x3d]	1737	1			T4	3		T22	1		T16	3
valid_sources[0x3e]	1486	1			T6	3		T28	2		T27	1
valid_sources[0x3f]	1492	1			T1	2		T6	3		T10	1
valid_sources[0x40]	2036	1			T3	1		T60	1		T16	3
valid_sources[0x41]	1629	1			T3	1		T25	2		T69	1
valid_sources[0x42]	1356	1			T28	1		T10	4		T16	1
valid_sources[0x43]	1874	1			T16	1		T39	1		T123	2
valid_sources[0x44]	1475	1			T16	1		T43	3		T18	4
valid_sources[0x45]	1810	1			T29	6		T16	3		T39	1
valid_sources[0x46]	1957	1			T3	2		T59	2		T16	2
valid_sources[0x47]	1694	1			T3	3		T123	1		T21	1
valid_sources[0x48]	1988	1			T3	1		T16	1		T43	2
valid_sources[0x49]	2353	1			T3	1		T10	1		T29	4
valid_sources[0x4a]	1318	1			T6	7		T15	11		T39	2
valid_sources[0x4b]	2280	1			T6	1		T10	1		T18	1
valid_sources[0x4c]	1450	1			T3	3		T16	7		T39	1
valid_sources[0x4d]	1829	1			T3	1		T6	3		T69	2
valid_sources[0x4e]	1448	1			T3	2		T6	2		T10	1
valid_sources[0x4f]	1665	1			T60	1		T15	1		T123	2
valid_sources[0x50]	1670	1			T3	3		T23	2		T6	2
valid_sources[0x51]	2003	1			T6	1		T71	2		T60	2
valid_sources[0x52]	1588	1			T3	1		T71	1		T60	1
valid_sources[0x53]	1730	1			T2	30		T22	1		T15	18
valid_sources[0x54]	2086	1			T59	1		T15	7		T27	1
valid_sources[0x55]	1969	1			T6	3		T9	1		T59	2
valid_sources[0x56]	2005	1			T6	1		T10	1		T68	1
valid_sources[0x57]	1611	1			T3	1		T16	1		T39	1
valid_sources[0x58]	1824	1			T6	1		T71	1		T25	2
valid_sources[0x59]	1401	1			T3	1		T68	1		T21	5
valid_sources[0x5a]	1707	1			T6	1		T25	2		T60	1
valid_sources[0x5b]	1652	1			T1	1		T16	1		T123	1
valid_sources[0x5c]	1726	1			T6	1		T68	1		T16	4
valid_sources[0x5d]	1609	1			T6	2		T9	1		T16	1
valid_sources[0x5e]	1523	1			T3	1		T60	1		T15	7
valid_sources[0x5f]	1711	1			T3	2		T6	2		T60	2
valid_sources[0x60]	2357	1			T3	1		T6	9		T9	1
valid_sources[0x61]	1607	1			T1	2		T3	1		T6	1
valid_sources[0x62]	2663	1			T23	2		T6	1		T16	1
valid_sources[0x63]	1984	1			T1	1		T6	2		T28	1
valid_sources[0x64]	1651	1			T3	1		T6	4		T71	1
valid_sources[0x65]	1540	1			T6	15		T9	2		T60	1
valid_sources[0x66]	1604	1			T6	1		T16	2		T21	1
valid_sources[0x67]	2082	1			T6	2		T9	3		T16	1
valid_sources[0x68]	1495	1			T6	2		T10	5		T16	5
valid_sources[0x69]	1534	1			T60	1		T16	1		T93	1
valid_sources[0x6a]	1746	1			T6	4		T60	1		T29	1
valid_sources[0x6b]	2038	1			T3	2		T71	1		T27	1
valid_sources[0x6c]	1682	1			T69	1		T16	2		T18	5
valid_sources[0x6d]	1960	1			T71	1		T59	2		T60	1
valid_sources[0x6e]	1433	1			T71	1		T60	1		T10	1
valid_sources[0x6f]	1900	1			T4	5		T60	1		T28	1
valid_sources[0x70]	1846	1			T3	2		T24	4		T60	1
valid_sources[0x71]	1755	1			T6	10		T16	8		T123	1
valid_sources[0x72]	1878	1			T25	1		T38	5		T16	1
valid_sources[0x73]	1721	1			T60	3		T123	1		T7	7
valid_sources[0x74]	1659	1			T17	5		T15	3		T69	1
valid_sources[0x75]	2074	1			T3	1		T6	4		T59	1
valid_sources[0x76]	1542	1			T6	1		T9	1		T71	1
valid_sources[0x77]	1925	1			T6	8		T59	1		T15	9
valid_sources[0x78]	1701	1			T22	1		T6	9		T93	3
valid_sources[0x79]	2922	1			T3	2		T6	1		T27	1
valid_sources[0x7a]	2930	1			T6	1		T10	2		T69	1
valid_sources[0x7b]	3051	1			T3	1		T10	3		T15	10
valid_sources[0x7c]	1643	1			T10	3		T16	1		T361	1
valid_sources[0x7d]	1534	1			T6	1		T9	1		T25	1
valid_sources[0x7e]	1519	1			T1	1		T6	1		T16	2
valid_sources[0x7f]	1485	1			T6	3		T71	1		T60	1
valid_sources[0x80]	1738	1			T3	2		T59	1		T68	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

80601

1

T1

5

T2

6

T3

3

values[0x0]

all_enables

biggest_size

110000

1

T1

2

T2

3

T3

9

values[0x1]

all_enables

biggest_size

108177

1

T1

2

T2

3

T3

13