Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2639	1			T4	3		T10	1		T30	2
non_zero_bins[1]	1991	1			T3	1		T4	1		T56	1
zero	9226	1			T1	3		T2	3		T3	6

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	494	1			T30	1		T56	1		T57	1
uni	3650	1			T1	1		T2	1		T3	2
gen	4450	1			T1	1		T2	1		T3	2
res	863	1			T3	1		T4	2		T10	1
ins	4399	1			T1	1		T2	1		T3	2

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

9062

1

T1

2

T2

3

T3

6

mubi_true

4794

1

T1

1

T3

1

T4

6

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

39

1

T29

1

T42

1

T100

1

pass

13817

1

T1

3

T2

3

T3

7

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	106	1			T30	1		T306	2		T37	1
upd	non_zero_bins[0]	pass	mubi_true	104	1			T57	1		T49	1		T119	1
upd	non_zero_bins[1]	pass	mubi_false	80	1			T307	1		T308	1		T44	1
upd	non_zero_bins[1]	pass	mubi_true	105	1			T56	1		T119	2		T108	1
upd	zero	pass	mubi_false	53	1			T72	1		T39	1		T236	1
upd	zero	pass	mubi_true	46	1			T308	1		T309	1		T310	2
uni	zero	pass	mubi_false	2703	1			T2	1		T3	2		T4	2
uni	zero	pass	mubi_true	947	1			T1	1		T4	1		T56	3
gen	non_zero_bins[0]	pass	mubi_false	467	1			T56	1		T15	4		T119	1
gen	non_zero_bins[0]	pass	mubi_true	565	1			T4	1		T57	2		T90	1
gen	non_zero_bins[1]	pass	mubi_false	400	1			T3	1		T22	3		T311	1
gen	non_zero_bins[1]	pass	mubi_true	365	1			T4	1		T57	1		T90	1
gen	zero	fail	mubi_false	32	1			T29	1		T42	1		T100	1
gen	zero	pass	mubi_false	1863	1			T1	1		T2	1		T4	1
gen	zero	pass	mubi_true	758	1			T3	1		T9	2		T24	2
res	non_zero_bins[0]	pass	mubi_false	189	1			T57	1		T77	1		T21	3
res	non_zero_bins[0]	pass	mubi_true	188	1			T4	1		T14	2		T15	2
res	non_zero_bins[1]	pass	mubi_false	139	1			T89	1		T46	1		T20	2
res	non_zero_bins[1]	pass	mubi_true	138	1			T312	1		T22	4		T119	1
res	zero	fail	mubi_false	7	1			T169	1		T170	1		T313	1
res	zero	pass	mubi_false	122	1			T3	1		T4	1		T10	1
res	zero	pass	mubi_true	80	1			T21	2		T54	1		T11	2
ins	non_zero_bins[0]	pass	mubi_false	505	1			T10	1		T56	2		T57	1
ins	non_zero_bins[0]	pass	mubi_true	515	1			T4	1		T30	1		T56	1
ins	non_zero_bins[1]	pass	mubi_false	370	1			T14	1		T21	2		T119	2
ins	non_zero_bins[1]	pass	mubi_true	394	1			T57	2		T89	1		T77	1
ins	zero	pass	mubi_false	2026	1			T1	1		T2	1		T3	2
ins	zero	pass	mubi_true	589	1			T4	1		T9	1		T10	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded