Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	1804	1			T3	1		T6	4		T9	1
non_zero_bins[1]	1274	1			T3	1		T6	4		T26	2
zero	6185	1			T1	3		T2	3		T3	3

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	301	1			T26	1		T127	1		T129	2
uni	2180	1			T1	1		T2	1		T3	2
gen	3196	1			T1	1		T2	1		T3	1
res	661	1			T6	2		T9	1		T14	3
ins	2925	1			T1	1		T2	1		T3	2

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

5921

1

T1

2

T2

3

T3

4

mubi_true

3342

1

T1

1

T3

1

T23

4

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

40

1

T58

1

T84

1

T96

1

pass

9223

1

T1

3

T2

3

T3

5

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	72	1			T47	1		T122	1		T115	1
upd	non_zero_bins[0]	pass	mubi_true	74	1			T127	1		T129	2		T124	1
upd	non_zero_bins[1]	pass	mubi_false	57	1			T216	1		T130	1		T299	1
upd	non_zero_bins[1]	pass	mubi_true	49	1			T26	1		T116	1		T299	1
upd	zero	pass	mubi_false	29	1			T35	1		T245	1		T217	3
upd	zero	pass	mubi_true	20	1			T116	1		T130	1		T300	1
uni	zero	pass	mubi_false	1646	1			T2	1		T3	2		T23	1
uni	zero	pass	mubi_true	534	1			T1	1		T6	1		T25	1
gen	non_zero_bins[0]	pass	mubi_false	356	1			T11	5		T61	2		T123	1
gen	non_zero_bins[0]	pass	mubi_true	379	1			T3	1		T11	1		T19	3
gen	non_zero_bins[1]	pass	mubi_false	253	1			T6	2		T26	1		T129	2
gen	non_zero_bins[1]	pass	mubi_true	221	1			T61	1		T123	1		T21	1
gen	zero	fail	mubi_false	37	1			T58	1		T84	1		T96	1
gen	zero	pass	mubi_false	1243	1			T1	1		T2	1		T4	1
gen	zero	pass	mubi_true	707	1			T23	3		T6	1		T24	2
res	non_zero_bins[0]	pass	mubi_false	155	1			T6	1		T9	1		T11	2
res	non_zero_bins[0]	pass	mubi_true	144	1			T6	1		T61	1		T43	1
res	non_zero_bins[1]	pass	mubi_false	103	1			T19	3		T90	4		T116	1
res	non_zero_bins[1]	pass	mubi_true	112	1			T14	3		T61	1		T129	1
res	zero	fail	mubi_false	3	1			T173	1		T301	1		T302	1
res	zero	pass	mubi_false	72	1			T61	1		T43	2		T136	1
res	zero	pass	mubi_true	72	1			T39	1		T21	2		T124	1
ins	non_zero_bins[0]	pass	mubi_false	307	1			T6	2		T26	1		T61	2
ins	non_zero_bins[0]	pass	mubi_true	317	1			T14	1		T19	1		T39	1
ins	non_zero_bins[1]	pass	mubi_false	250	1			T3	1		T14	1		T61	3
ins	non_zero_bins[1]	pass	mubi_true	229	1			T6	2		T11	1		T61	2
ins	zero	pass	mubi_false	1338	1			T1	1		T2	1		T3	1
ins	zero	pass	mubi_true	484	1			T23	1		T24	2		T9	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded