Module Definition
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Module : prim_fifo_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd 92.86 100.00 71.43 100.00 100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd 94.64 100.00 78.57 100.00 100.00


Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.86 100.00 71.43 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.84 100.00 89.19 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.31 100.00 91.03 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.38 100.00 91.89 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.31 100.00 91.03 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_fifo_sync
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN14011100.00


68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108                           assign storage_rdata = storage[0];
109                     
110                           always_ff @(posedge clk_i)
111                             if (fifo_incr_wptr) begin
112                               storage[0] <= wdata_i;
113                             end
114                     
115                           logic unused_ptrs;
116                           assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120        1/1                assign storage_rdata = storage[fifo_rptr];
           Tests:       T1 T2 T3 
121                     
122                           always_ff @(posedge clk_i)
123        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
124        1/1                    storage[fifo_wptr] <= wdata_i;
           Tests:       T5 T9 T17 
125                             end
                        MISSING_ELSE
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T5 T9 T17 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138                           assign rdata_o = empty ? Width'(0) : rdata_int;
139                         end else begin : gen_no_output_zero
140        1/1                assign rdata_o = rdata_int;
           Tests:       T5 T9 T17 
Cond Coverage for Module : prim_fifo_sync
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT5,T9,T10
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT5,T9,T17 

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT110
110Not Covered
111CoveredT5,T9,T17 

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT29,T33,T34
101CoveredT5,T9,T17
110Not Covered
111CoveredT9,T14,T11
Branch Coverage for Module : prim_fifo_sync
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00 



69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



123                if (fifo_incr_wptr) begin
                   -1-     
124                  storage[fifo_wptr] <= wdata_i;
                     ==>
125                end
                   MISSING_ELSE
                   ==>

Branches:
-1-StatusTests
1 Covered T5,T9,T17
0 Covered T1,T2,T3

Assert Coverage for Module : prim_fifo_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 21114680 1056683 0 0
DataKnown_AKnownEnable 21896466 21527724 0 0
DepthKnown_A 21896466 21527724 0 0
RvalidKnown_A 21896466 21527724 0 0
WreadyKnown_A 21896466 21527724 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 21508808 1165122 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 21114680 1056683 0 0
T5 938 425 0 0
T6 31036 0 0 0
T7 0 75 0 0
T9 5524 5149 0 0
T10 0 547 0 0
T11 0 3875 0 0
T14 0 4504 0 0
T19 0 2444 0 0
T21 0 1613 0 0
T22 1500 0 0 0
T23 3484 0 0 0
T24 2442 0 0 0
T25 3266 0 0 0
T43 0 4725 0 0
T56 0 767 0 0
T59 3274 0 0 0
T60 8392 0 0 0
T71 2964 0 0 0

DataKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 21896466 21527724 0 0
T1 2224 2106 0 0
T2 2002 1848 0 0
T3 2800 2658 0 0
T4 4022 3704 0 0
T5 2606 2344 0 0
T6 31036 30040 0 0
T9 5524 5356 0 0
T22 1500 1362 0 0
T23 3484 3376 0 0
T24 2442 2264 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 21896466 21527724 0 0
T1 2224 2106 0 0
T2 2002 1848 0 0
T3 2800 2658 0 0
T4 4022 3704 0 0
T5 2606 2344 0 0
T6 31036 30040 0 0
T9 5524 5356 0 0
T22 1500 1362 0 0
T23 3484 3376 0 0
T24 2442 2264 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 21896466 21527724 0 0
T1 2224 2106 0 0
T2 2002 1848 0 0
T3 2800 2658 0 0
T4 4022 3704 0 0
T5 2606 2344 0 0
T6 31036 30040 0 0
T9 5524 5356 0 0
T22 1500 1362 0 0
T23 3484 3376 0 0
T24 2442 2264 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 21896466 21527724 0 0
T1 2224 2106 0 0
T2 2002 1848 0 0
T3 2800 2658 0 0
T4 4022 3704 0 0
T5 2606 2344 0 0
T6 31036 30040 0 0
T9 5524 5356 0 0
T22 1500 1362 0 0
T23 3484 3376 0 0
T24 2442 2264 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 21508808 1165122 0 0
T5 2606 1247 0 0
T6 31036 0 0 0
T7 0 920 0 0
T9 5524 5149 0 0
T10 0 547 0 0
T11 0 3875 0 0
T14 0 4504 0 0
T17 0 2290 0 0
T19 0 2444 0 0
T22 1500 0 0 0
T23 3484 0 0 0
T24 2442 0 0 0
T25 3266 0 0 0
T43 0 4725 0 0
T59 3274 0 0 0
T60 8392 0 0 0
T71 2964 0 0 0
T72 0 220 0 0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN14011100.00


68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108                           assign storage_rdata = storage[0];
109                     
110                           always_ff @(posedge clk_i)
111                             if (fifo_incr_wptr) begin
112                               storage[0] <= wdata_i;
113                             end
114                     
115                           logic unused_ptrs;
116                           assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120        1/1                assign storage_rdata = storage[fifo_rptr];
           Tests:       T1 T2 T3 
121                     
122                           always_ff @(posedge clk_i)
123        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
124        1/1                    storage[fifo_wptr] <= wdata_i;
           Tests:       T5 T9 T17 
125                             end
                        MISSING_ELSE
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T5 T9 T17 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138                           assign rdata_o = empty ? Width'(0) : rdata_int;
139                         end else begin : gen_no_output_zero
140        1/1                assign rdata_o = rdata_int;
           Tests:       T5 T9 T17 
Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
TotalCoveredPercent
Conditions141071.43
Logical141071.43
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT5,T63,T82
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT5,T9,T17 

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT5,T9,T17 

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT33,T34,T53
101CoveredT5,T9,T17
110Not Covered
111CoveredT9,T14,T11
Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00 



69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



123                if (fifo_incr_wptr) begin
                   -1-     
124                  storage[fifo_wptr] <= wdata_i;
                     ==>
125                end
                   MISSING_ELSE
                   ==>

Branches:
-1-StatusTests
1 Covered T5,T9,T17
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 10557340 522185 0 0
DataKnown_AKnownEnable 10948233 10763862 0 0
DepthKnown_A 10948233 10763862 0 0
RvalidKnown_A 10948233 10763862 0 0
WreadyKnown_A 10948233 10763862 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 10754404 576039 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10557340 522185 0 0
T5 469 222 0 0
T6 15518 0 0 0
T7 0 25 0 0
T9 2762 2549 0 0
T10 0 262 0 0
T11 0 1883 0 0
T14 0 2238 0 0
T19 0 1217 0 0
T21 0 793 0 0
T22 750 0 0 0
T23 1742 0 0 0
T24 1221 0 0 0
T25 1633 0 0 0
T43 0 2342 0 0
T56 0 378 0 0
T59 1637 0 0 0
T60 4196 0 0 0
T71 1482 0 0 0

DataKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 10948233 10763862 0 0
T1 1112 1053 0 0
T2 1001 924 0 0
T3 1400 1329 0 0
T4 2011 1852 0 0
T5 1303 1172 0 0
T6 15518 15020 0 0
T9 2762 2678 0 0
T22 750 681 0 0
T23 1742 1688 0 0
T24 1221 1132 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10948233 10763862 0 0
T1 1112 1053 0 0
T2 1001 924 0 0
T3 1400 1329 0 0
T4 2011 1852 0 0
T5 1303 1172 0 0
T6 15518 15020 0 0
T9 2762 2678 0 0
T22 750 681 0 0
T23 1742 1688 0 0
T24 1221 1132 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10948233 10763862 0 0
T1 1112 1053 0 0
T2 1001 924 0 0
T3 1400 1329 0 0
T4 2011 1852 0 0
T5 1303 1172 0 0
T6 15518 15020 0 0
T9 2762 2678 0 0
T22 750 681 0 0
T23 1742 1688 0 0
T24 1221 1132 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10948233 10763862 0 0
T1 1112 1053 0 0
T2 1001 924 0 0
T3 1400 1329 0 0
T4 2011 1852 0 0
T5 1303 1172 0 0
T6 15518 15020 0 0
T9 2762 2678 0 0
T22 750 681 0 0
T23 1742 1688 0 0
T24 1221 1132 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 10754404 576039 0 0
T5 1303 582 0 0
T6 15518 0 0 0
T7 0 491 0 0
T9 2762 2549 0 0
T10 0 262 0 0
T11 0 1883 0 0
T14 0 2238 0 0
T17 0 1149 0 0
T19 0 1217 0 0
T22 750 0 0 0
T23 1742 0 0 0
T24 1221 0 0 0
T25 1633 0 0 0
T43 0 2342 0 0
T59 1637 0 0 0
T60 4196 0 0 0
T71 1482 0 0 0
T72 0 111 0 0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN14011100.00


68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108                           assign storage_rdata = storage[0];
109                     
110                           always_ff @(posedge clk_i)
111                             if (fifo_incr_wptr) begin
112                               storage[0] <= wdata_i;
113                             end
114                     
115                           logic unused_ptrs;
116                           assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120        1/1                assign storage_rdata = storage[fifo_rptr];
           Tests:       T1 T2 T3 
121                     
122                           always_ff @(posedge clk_i)
123        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
124        1/1                    storage[fifo_wptr] <= wdata_i;
           Tests:       T5 T9 T17 
125                             end
                        MISSING_ELSE
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T5 T9 T17 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138                           assign rdata_o = empty ? Width'(0) : rdata_int;
139                         end else begin : gen_no_output_zero
140        1/1                assign rdata_o = rdata_int;
           Tests:       T5 T9 T17 
Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT5,T9,T10
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT5,T9,T17 

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT110
110Not Covered
111CoveredT5,T9,T17 

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT29,T111,T112
101CoveredT5,T9,T17
110Not Covered
111CoveredT9,T14,T11
Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00 



69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



123                if (fifo_incr_wptr) begin
                   -1-     
124                  storage[fifo_wptr] <= wdata_i;
                     ==>
125                end
                   MISSING_ELSE
                   ==>

Branches:
-1-StatusTests
1 Covered T5,T9,T17
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 10557340 534498 0 0
DataKnown_AKnownEnable 10948233 10763862 0 0
DepthKnown_A 10948233 10763862 0 0
RvalidKnown_A 10948233 10763862 0 0
WreadyKnown_A 10948233 10763862 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 10754404 589083 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10557340 534498 0 0
T5 469 203 0 0
T6 15518 0 0 0
T7 0 50 0 0
T9 2762 2600 0 0
T10 0 285 0 0
T11 0 1992 0 0
T14 0 2266 0 0
T19 0 1227 0 0
T21 0 820 0 0
T22 750 0 0 0
T23 1742 0 0 0
T24 1221 0 0 0
T25 1633 0 0 0
T43 0 2383 0 0
T56 0 389 0 0
T59 1637 0 0 0
T60 4196 0 0 0
T71 1482 0 0 0

DataKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 10948233 10763862 0 0
T1 1112 1053 0 0
T2 1001 924 0 0
T3 1400 1329 0 0
T4 2011 1852 0 0
T5 1303 1172 0 0
T6 15518 15020 0 0
T9 2762 2678 0 0
T22 750 681 0 0
T23 1742 1688 0 0
T24 1221 1132 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10948233 10763862 0 0
T1 1112 1053 0 0
T2 1001 924 0 0
T3 1400 1329 0 0
T4 2011 1852 0 0
T5 1303 1172 0 0
T6 15518 15020 0 0
T9 2762 2678 0 0
T22 750 681 0 0
T23 1742 1688 0 0
T24 1221 1132 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10948233 10763862 0 0
T1 1112 1053 0 0
T2 1001 924 0 0
T3 1400 1329 0 0
T4 2011 1852 0 0
T5 1303 1172 0 0
T6 15518 15020 0 0
T9 2762 2678 0 0
T22 750 681 0 0
T23 1742 1688 0 0
T24 1221 1132 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10948233 10763862 0 0
T1 1112 1053 0 0
T2 1001 924 0 0
T3 1400 1329 0 0
T4 2011 1852 0 0
T5 1303 1172 0 0
T6 15518 15020 0 0
T9 2762 2678 0 0
T22 750 681 0 0
T23 1742 1688 0 0
T24 1221 1132 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 10754404 589083 0 0
T5 1303 665 0 0
T6 15518 0 0 0
T7 0 429 0 0
T9 2762 2600 0 0
T10 0 285 0 0
T11 0 1992 0 0
T14 0 2266 0 0
T17 0 1141 0 0
T19 0 1227 0 0
T22 750 0 0 0
T23 1742 0 0 0
T24 1221 0 0 0
T25 1633 0 0 0
T43 0 2383 0 0
T59 1637 0 0 0
T60 4196 0 0 0
T71 1482 0 0 0
T72 0 109 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%