Module Definition
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Module : prim_packer_fifo
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.81 100.00 95.24 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_edn_core.u_prim_packer_fifo_cs 95.24 100.00 95.24 85.71 100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep 98.81 100.00 95.24 100.00 100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep 98.81 100.00 95.24 100.00 100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep 98.81 100.00 95.24 100.00 100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep 98.81 100.00 95.24 100.00 100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep 98.81 100.00 95.24 100.00 100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep 98.81 100.00 95.24 100.00 100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep 98.81 100.00 95.24 100.00 100.00


Module Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.24 100.00 95.24 85.71 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.24 100.00 95.24 85.71 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.31 100.00 91.03 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.81 100.00 95.24 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.81 100.00 95.24 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.31 100.00 91.03 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.81 100.00 95.24 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.81 100.00 95.24 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.31 100.00 91.03 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.81 100.00 95.24 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.81 100.00 95.24 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.31 100.00 91.03 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.81 100.00 95.24 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.81 100.00 95.24 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.31 100.00 91.03 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.81 100.00 95.24 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.81 100.00 95.24 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.31 100.00 91.03 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.81 100.00 95.24 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.81 100.00 95.24 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.31 100.00 91.03 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.81 100.00 95.24 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.81 100.00 95.24 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.31 100.00 91.03 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_packer_fifo ( parameter InW=128,OutW=128,ClearOnRead=0,MaxW=128,MinW=128,DepthW=0 )
Line Coverage for Module self-instances :
SCORELINE
95.24 100.00
tb.dut.u_edn_core.u_prim_packer_fifo_cs

Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS8277100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9611100.00
ALWAYS12733100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15811100.00


81                        always_ff @(posedge clk_i or negedge rst_ni) begin
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                depth_q <= '0;
           Tests:       T1 T2 T3 
84         1/1                data_q  <= '0;
           Tests:       T1 T2 T3 
85         1/1                clr_q   <= 1'b1;
           Tests:       T1 T2 T3 
86                          end else begin
87         1/1                depth_q <= depth_d;
           Tests:       T1 T2 T3 
88         1/1                data_q  <= data_d;
           Tests:       T1 T2 T3 
89         1/1                clr_q   <= clr_d;
           Tests:       T1 T2 T3 
90                          end
91                        end
92                      
93                        // flop for handling reset case for clr
94         1/1            assign clr_d = clr_i;
           Tests:       T1 T2 T3 
95                      
96         1/1            assign depth_o = depth_q;
           Tests:       T1 T2 T3 
97                      
98                        if (InW < OutW) begin : gen_pack_mode
99                          logic [MaxW-1:0] wdata_shifted;
100                     
101                         assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW);
102                         assign clear_status = (rready_i && rvalid_o) || clr_q;
103                         assign clear_data = (ClearOnRead && clear_status) || clr_q;
104                         assign load_data = wvalid_i && wready_o;
105                     
106                         assign depth_d =  clear_status ? '0 :
107                                load_data ? (depth_q + DepthOne):
108                                depth_q;
109                     
110                         assign data_d = clear_data ? '0 :
111                                load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) :
112                                data_q;
113                     
114                         // set outputs
115                         assign wready_o = !(depth_q == FullDepth) && !clr_q;
116                         assign rdata_o =  data_q;
117                         assign rvalid_o = (depth_q == FullDepth) && !clr_q;
118                     
119                       end else begin : gen_unpack_mode
120                         logic [MaxW-1:0] rdata_shifted;
121                         logic            pull_data;
122                         logic [DepthW:0] ptr_q, ptr_d;
123                         logic [DepthW:0] lsb_is_one;
124                         logic [DepthW:0] max_value;
125                     
126                         always_ff @(posedge clk_i or negedge rst_ni) begin
127        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
128        1/1                  ptr_q   <= '0;
           Tests:       T1 T2 T3 
129                           end else begin
130        1/1                  ptr_q   <= ptr_d;
           Tests:       T1 T2 T3 
131                           end
132                         end
133                     
134                         assign lsb_is_one = {{DepthW{1'b0}},1'b1};
135                         assign max_value = FullDepth;
136        1/1              assign rdata_shifted = data_q >> ptr_q*OutW;
           Tests:       T1 T2 T3 
137        1/1              assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q;
           Tests:       T1 T2 T3 
138        1/1              assign clear_data = (ClearOnRead && clear_status) || clr_q;
           Tests:       T1 T2 T3 
139        1/1              assign load_data = wvalid_i && wready_o;
           Tests:       T1 T2 T3 
140        1/1              assign pull_data = rvalid_o && rready_i;
           Tests:       T1 T2 T3 
141                     
142        1/1              assign depth_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
143                                load_data ? max_value :
144                                pull_data ? (depth_q - DepthOne) :
145                                depth_q;
146                     
147        1/1              assign ptr_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
148                                pull_data ? (ptr_q + DepthOne) :
149                                ptr_q;
150                     
151        1/1              assign data_d = clear_data ? '0 :
           Tests:       T1 T2 T3 
152                                load_data ? wdata_i :
153                                data_q;
154                     
155                         // set outputs
156        1/1              assign wready_o = (depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
157        1/1              assign rdata_o =  rdata_shifted[OutW-1:0];
           Tests:       T1 T2 T3 
158        1/1              assign rvalid_o = !(depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
Line Coverage for Module : prim_packer_fifo ( parameter InW=128,OutW=32,ClearOnRead=0,MaxW=128,MinW=32,DepthW=2 )
Line Coverage for Module self-instances :
SCORELINE
98.81 100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep

SCORELINE
98.81 100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep

SCORELINE
98.81 100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep

SCORELINE
98.81 100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep

SCORELINE
98.81 100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep

SCORELINE
98.81 100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep

SCORELINE
98.81 100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep

Line No.TotalCoveredPercent
TOTAL2424100.00
ALWAYS8277100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9611100.00
ALWAYS12733100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN16311100.00


81                        always_ff @(posedge clk_i or negedge rst_ni) begin
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                depth_q <= '0;
           Tests:       T1 T2 T3 
84         1/1                data_q  <= '0;
           Tests:       T1 T2 T3 
85         1/1                clr_q   <= 1'b1;
           Tests:       T1 T2 T3 
86                          end else begin
87         1/1                depth_q <= depth_d;
           Tests:       T1 T2 T3 
88         1/1                data_q  <= data_d;
           Tests:       T1 T2 T3 
89         1/1                clr_q   <= clr_d;
           Tests:       T1 T2 T3 
90                          end
91                        end
92                      
93                        // flop for handling reset case for clr
94         1/1            assign clr_d = clr_i;
           Tests:       T1 T2 T3 
95                      
96         1/1            assign depth_o = depth_q;
           Tests:       T1 T2 T3 
97                      
98                        if (InW < OutW) begin : gen_pack_mode
99                          logic [MaxW-1:0] wdata_shifted;
100                     
101                         assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW);
102                         assign clear_status = (rready_i && rvalid_o) || clr_q;
103                         assign clear_data = (ClearOnRead && clear_status) || clr_q;
104                         assign load_data = wvalid_i && wready_o;
105                     
106                         assign depth_d =  clear_status ? '0 :
107                                load_data ? (depth_q + DepthOne):
108                                depth_q;
109                     
110                         assign data_d = clear_data ? '0 :
111                                load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) :
112                                data_q;
113                     
114                         // set outputs
115                         assign wready_o = !(depth_q == FullDepth) && !clr_q;
116                         assign rdata_o =  data_q;
117                         assign rvalid_o = (depth_q == FullDepth) && !clr_q;
118                     
119                       end else begin : gen_unpack_mode
120                         logic [MaxW-1:0] rdata_shifted;
121                         logic            pull_data;
122                         logic [DepthW:0] ptr_q, ptr_d;
123                         logic [DepthW:0] lsb_is_one;
124                         logic [DepthW:0] max_value;
125                     
126                         always_ff @(posedge clk_i or negedge rst_ni) begin
127        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
128        1/1                  ptr_q   <= '0;
           Tests:       T1 T2 T3 
129                           end else begin
130        1/1                  ptr_q   <= ptr_d;
           Tests:       T1 T2 T3 
131                           end
132                         end
133                     
134                         assign lsb_is_one = {{DepthW{1'b0}},1'b1};
135                         assign max_value = FullDepth;
136        1/1              assign rdata_shifted = data_q >> ptr_q*OutW;
           Tests:       T1 T2 T3 
137        1/1              assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q;
           Tests:       T1 T2 T3 
138        1/1              assign clear_data = (ClearOnRead && clear_status) || clr_q;
           Tests:       T1 T2 T3 
139        1/1              assign load_data = wvalid_i && wready_o;
           Tests:       T1 T2 T3 
140        1/1              assign pull_data = rvalid_o && rready_i;
           Tests:       T1 T2 T3 
141                     
142        1/1              assign depth_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
143                                load_data ? max_value :
144                                pull_data ? (depth_q - DepthOne) :
145                                depth_q;
146                     
147        1/1              assign ptr_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
148                                pull_data ? (ptr_q + DepthOne) :
149                                ptr_q;
150                     
151        1/1              assign data_d = clear_data ? '0 :
           Tests:       T1 T2 T3 
152                                load_data ? wdata_i :
153                                data_q;
154                     
155                         // set outputs
156        1/1              assign wready_o = (depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
157        1/1              assign rdata_o =  rdata_shifted[OutW-1:0];
           Tests:       T1 T2 T3 
158        1/1              assign rvalid_o = !(depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
159                     
160                         // Avoid possible lint errors in case InW > OutW.
161                         if (InW > OutW) begin : gen_unused
162                           logic [MaxW-MinW-1:0] unused_rdata_shifted;
163        1/1                assign unused_rdata_shifted = rdata_shifted[MaxW-1:MinW];
           Tests:       T1 T2 T3 
Cond Coverage for Module : prim_packer_fifo ( parameter InW=128,OutW=128,ClearOnRead=0,MaxW=128,MinW=128,DepthW=0 )
Cond Coverage for Module self-instances :
SCORECOND
95.24 95.24
tb.dut.u_edn_core.u_prim_packer_fifo_cs

TotalCoveredPercent
Conditions424095.24
Logical424095.24
Non-Logical00
Event00

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3 

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------
-1--2-StatusTests
01CoveredT4,T23,T24
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable 

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T23,T24
11CoveredT1,T2,T3 

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered 

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered 

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT14,T19,T43
11CoveredT1,T2,T3 

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3
Cond Coverage for Module : prim_packer_fifo ( parameter InW=128,OutW=32,ClearOnRead=0,MaxW=128,MinW=32,DepthW=2 )
Cond Coverage for Module self-instances :
SCORECOND
98.81 95.24
tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep

SCORECOND
98.81 95.24
tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep

SCORECOND
98.81 95.24
tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep

SCORECOND
98.81 95.24
tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep

SCORECOND
98.81 95.24
tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep

SCORECOND
98.81 95.24
tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep

SCORECOND
98.81 95.24
tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep

TotalCoveredPercent
Conditions424095.24
Logical424095.24
Non-Logical00
Event00

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3 

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable 

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3 

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT23,T46,T54
11CoveredT1,T2,T3 

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3
Branch Coverage for Module : prim_packer_fifo
Line No.TotalCoveredPercent
Branches 14 14 100.00
TERNARY 142 4 4 100.00
TERNARY 147 3 3 100.00
TERNARY 151 3 3 100.00
IF 82 2 2 100.00
IF 127 2 2 100.00 



142            assign depth_d =  clear_status ? '0 :
                                              -1-  
                                              ==>  
143                   load_data ? max_value :
                                -2-  
                                ==>  
144                   pull_data ? (depth_q - DepthOne) :
                                -3-  
                                ==>  
                                ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3 



147            assign ptr_d =  clear_status ? '0 :
                                            -1-  
                                            ==>  
148                   pull_data ? (ptr_q + DepthOne) :
                                -2-  
                                ==>  
                                ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



151            assign data_d = clear_data ? '0 :
                                          -1-  
                                          ==>  
152                   load_data ? wdata_i :
                                -2-  
                                ==>  
                                ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



82             if (!rst_ni) begin
               -1-  
83               depth_q <= '0;
                 ==>
84               data_q  <= '0;
85               clr_q   <= 1'b1;
86             end else begin
87               depth_q <= depth_d;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



127              if (!rst_ni) begin
                 -1-  
128                ptr_q   <= '0;
                   ==>
129              end else begin
130                ptr_q   <= ptr_d;
                   ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Assert Coverage for Module : prim_packer_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataOStableWhenPending_A 87585864 9020195 0 7464
ValidOPairedWithReadyI_A 87585864 9020195 0 0


DataOStableWhenPending_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 87585864 9020195 0 7464
T1 1112 883 0 1
T2 1001 740 0 1
T3 1400 797 0 1
T4 2011 987 0 1
T5 1303 0 0 1
T6 15518 8644 0 1
T9 2762 0 0 1
T11 4152 0 0 1
T14 6914 938 0 2
T19 2271 0 0 1
T22 750 0 0 1
T23 1742 1062 0 1
T24 1221 0 0 1
T25 0 1183 0 0
T26 4529 7126 0 1
T27 2501 0 0 1
T28 0 861 0 0
T29 1255 0 0 1
T38 0 996 0 0
T39 0 1174 0 0
T40 0 360 0 0
T41 0 879 0 0
T42 0 1420 0 0
T46 915 0 0 1
T47 0 4513 0 0
T67 2418 0 0 2
T68 3728 0 0 2
T69 2206 0 0 2
T71 0 1235 0 0
T72 1876 0 0 1
T74 0 1131 0 0
T75 0 1073 0 0
T76 0 136 0 0
T77 0 5089 0 0

ValidOPairedWithReadyI_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 87585864 9020195 0 0
T1 1112 883 0 0
T2 1001 740 0 0
T3 1400 797 0 0
T4 2011 987 0 0
T5 1303 0 0 0
T6 15518 8644 0 0
T9 2762 0 0 0
T11 4152 0 0 0
T14 6914 938 0 0
T19 2271 0 0 0
T22 750 0 0 0
T23 1742 1062 0 0
T24 1221 0 0 0
T25 0 1183 0 0
T26 4529 7126 0 0
T27 2501 0 0 0
T28 0 861 0 0
T29 1255 0 0 0
T38 0 996 0 0
T39 0 1174 0 0
T40 0 360 0 0
T41 0 879 0 0
T42 0 1420 0 0
T46 915 0 0 0
T47 0 4513 0 0
T67 2418 0 0 0
T68 3728 0 0 0
T69 2206 0 0 0
T71 0 1235 0 0
T72 1876 0 0 0
T74 0 1131 0 0
T75 0 1073 0 0
T76 0 136 0 0
T77 0 5089 0 0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS8277100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9611100.00
ALWAYS12733100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15811100.00


81                        always_ff @(posedge clk_i or negedge rst_ni) begin
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                depth_q <= '0;
           Tests:       T1 T2 T3 
84         1/1                data_q  <= '0;
           Tests:       T1 T2 T3 
85         1/1                clr_q   <= 1'b1;
           Tests:       T1 T2 T3 
86                          end else begin
87         1/1                depth_q <= depth_d;
           Tests:       T1 T2 T3 
88         1/1                data_q  <= data_d;
           Tests:       T1 T2 T3 
89         1/1                clr_q   <= clr_d;
           Tests:       T1 T2 T3 
90                          end
91                        end
92                      
93                        // flop for handling reset case for clr
94         1/1            assign clr_d = clr_i;
           Tests:       T1 T2 T3 
95                      
96         1/1            assign depth_o = depth_q;
           Tests:       T1 T2 T3 
97                      
98                        if (InW < OutW) begin : gen_pack_mode
99                          logic [MaxW-1:0] wdata_shifted;
100                     
101                         assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW);
102                         assign clear_status = (rready_i && rvalid_o) || clr_q;
103                         assign clear_data = (ClearOnRead && clear_status) || clr_q;
104                         assign load_data = wvalid_i && wready_o;
105                     
106                         assign depth_d =  clear_status ? '0 :
107                                load_data ? (depth_q + DepthOne):
108                                depth_q;
109                     
110                         assign data_d = clear_data ? '0 :
111                                load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) :
112                                data_q;
113                     
114                         // set outputs
115                         assign wready_o = !(depth_q == FullDepth) && !clr_q;
116                         assign rdata_o =  data_q;
117                         assign rvalid_o = (depth_q == FullDepth) && !clr_q;
118                     
119                       end else begin : gen_unpack_mode
120                         logic [MaxW-1:0] rdata_shifted;
121                         logic            pull_data;
122                         logic [DepthW:0] ptr_q, ptr_d;
123                         logic [DepthW:0] lsb_is_one;
124                         logic [DepthW:0] max_value;
125                     
126                         always_ff @(posedge clk_i or negedge rst_ni) begin
127        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
128        1/1                  ptr_q   <= '0;
           Tests:       T1 T2 T3 
129                           end else begin
130        1/1                  ptr_q   <= ptr_d;
           Tests:       T1 T2 T3 
131                           end
132                         end
133                     
134                         assign lsb_is_one = {{DepthW{1'b0}},1'b1};
135                         assign max_value = FullDepth;
136        1/1              assign rdata_shifted = data_q >> ptr_q*OutW;
           Tests:       T1 T2 T3 
137        1/1              assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q;
           Tests:       T1 T2 T3 
138        1/1              assign clear_data = (ClearOnRead && clear_status) || clr_q;
           Tests:       T1 T2 T3 
139        1/1              assign load_data = wvalid_i && wready_o;
           Tests:       T1 T2 T3 
140        1/1              assign pull_data = rvalid_o && rready_i;
           Tests:       T1 T2 T3 
141                     
142        1/1              assign depth_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
143                                load_data ? max_value :
144                                pull_data ? (depth_q - DepthOne) :
145                                depth_q;
146                     
147        1/1              assign ptr_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
148                                pull_data ? (ptr_q + DepthOne) :
149                                ptr_q;
150                     
151        1/1              assign data_d = clear_data ? '0 :
           Tests:       T1 T2 T3 
152                                load_data ? wdata_i :
153                                data_q;
154                     
155                         // set outputs
156        1/1              assign wready_o = (depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
157        1/1              assign rdata_o =  rdata_shifted[OutW-1:0];
           Tests:       T1 T2 T3 
158        1/1              assign rvalid_o = !(depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs
TotalCoveredPercent
Conditions424095.24
Logical424095.24
Non-Logical00
Event00

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3 

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------
-1--2-StatusTests
01CoveredT4,T23,T24
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable 

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T23,T24
11CoveredT1,T2,T3 

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered 

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered 

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT14,T19,T43
11CoveredT1,T2,T3 

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs
Line No.TotalCoveredPercent
Branches 14 12 85.71
TERNARY 142 4 3 75.00
TERNARY 147 3 2 66.67
TERNARY 151 3 3 100.00
IF 82 2 2 100.00
IF 127 2 2 100.00 



142            assign depth_d =  clear_status ? '0 :
                                              -1-  
                                              ==>  
143                   load_data ? max_value :
                                -2-  
                                ==>  
144                   pull_data ? (depth_q - DepthOne) :
                                -3-  
                                ==>  
                                ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3 



147            assign ptr_d =  clear_status ? '0 :
                                            -1-  
                                            ==>  
148                   pull_data ? (ptr_q + DepthOne) :
                                -2-  
                                ==>  
                                ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3 



151            assign data_d = clear_data ? '0 :
                                          -1-  
                                          ==>  
152                   load_data ? wdata_i :
                                -2-  
                                ==>  
                                ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



82             if (!rst_ni) begin
               -1-  
83               depth_q <= '0;
                 ==>
84               data_q  <= '0;
85               clr_q   <= 1'b1;
86             end else begin
87               depth_q <= depth_d;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



127              if (!rst_ni) begin
                 -1-  
128                ptr_q   <= '0;
                   ==>
129              end else begin
130                ptr_q   <= ptr_d;
                   ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataOStableWhenPending_A 10948233 121446 0 933
ValidOPairedWithReadyI_A 10948233 121446 0 0


DataOStableWhenPending_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10948233 121446 0 933
T4 2011 26 0 1
T5 1303 0 0 1
T6 15518 0 0 1
T9 2762 2263 0 1
T10 0 28 0 0
T11 0 1 0 0
T14 0 365 0 0
T19 0 573 0 0
T22 750 0 0 1
T23 1742 57 0 1
T24 1221 773 0 1
T25 1633 0 0 1
T28 0 63 0 0
T29 0 32 0 0
T59 1637 0 0 1
T71 1482 0 0 1

ValidOPairedWithReadyI_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10948233 121446 0 0
T4 2011 26 0 0
T5 1303 0 0 0
T6 15518 0 0 0
T9 2762 2263 0 0
T10 0 28 0 0
T11 0 1 0 0
T14 0 365 0 0
T19 0 573 0 0
T22 750 0 0 0
T23 1742 57 0 0
T24 1221 773 0 0
T25 1633 0 0 0
T28 0 63 0 0
T29 0 32 0 0
T59 1637 0 0 0
T71 1482 0 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep
Line No.TotalCoveredPercent
TOTAL2424100.00
ALWAYS8277100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9611100.00
ALWAYS12733100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN16311100.00


81                        always_ff @(posedge clk_i or negedge rst_ni) begin
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                depth_q <= '0;
           Tests:       T1 T2 T3 
84         1/1                data_q  <= '0;
           Tests:       T1 T2 T3 
85         1/1                clr_q   <= 1'b1;
           Tests:       T1 T2 T3 
86                          end else begin
87         1/1                depth_q <= depth_d;
           Tests:       T1 T2 T3 
88         1/1                data_q  <= data_d;
           Tests:       T1 T2 T3 
89         1/1                clr_q   <= clr_d;
           Tests:       T1 T2 T3 
90                          end
91                        end
92                      
93                        // flop for handling reset case for clr
94         1/1            assign clr_d = clr_i;
           Tests:       T1 T2 T3 
95                      
96         1/1            assign depth_o = depth_q;
           Tests:       T1 T2 T3 
97                      
98                        if (InW < OutW) begin : gen_pack_mode
99                          logic [MaxW-1:0] wdata_shifted;
100                     
101                         assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW);
102                         assign clear_status = (rready_i && rvalid_o) || clr_q;
103                         assign clear_data = (ClearOnRead && clear_status) || clr_q;
104                         assign load_data = wvalid_i && wready_o;
105                     
106                         assign depth_d =  clear_status ? '0 :
107                                load_data ? (depth_q + DepthOne):
108                                depth_q;
109                     
110                         assign data_d = clear_data ? '0 :
111                                load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) :
112                                data_q;
113                     
114                         // set outputs
115                         assign wready_o = !(depth_q == FullDepth) && !clr_q;
116                         assign rdata_o =  data_q;
117                         assign rvalid_o = (depth_q == FullDepth) && !clr_q;
118                     
119                       end else begin : gen_unpack_mode
120                         logic [MaxW-1:0] rdata_shifted;
121                         logic            pull_data;
122                         logic [DepthW:0] ptr_q, ptr_d;
123                         logic [DepthW:0] lsb_is_one;
124                         logic [DepthW:0] max_value;
125                     
126                         always_ff @(posedge clk_i or negedge rst_ni) begin
127        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
128        1/1                  ptr_q   <= '0;
           Tests:       T1 T2 T3 
129                           end else begin
130        1/1                  ptr_q   <= ptr_d;
           Tests:       T1 T2 T3 
131                           end
132                         end
133                     
134                         assign lsb_is_one = {{DepthW{1'b0}},1'b1};
135                         assign max_value = FullDepth;
136        1/1              assign rdata_shifted = data_q >> ptr_q*OutW;
           Tests:       T1 T2 T3 
137        1/1              assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q;
           Tests:       T1 T2 T3 
138        1/1              assign clear_data = (ClearOnRead && clear_status) || clr_q;
           Tests:       T1 T2 T3 
139        1/1              assign load_data = wvalid_i && wready_o;
           Tests:       T1 T2 T3 
140        1/1              assign pull_data = rvalid_o && rready_i;
           Tests:       T1 T2 T3 
141                     
142        1/1              assign depth_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
143                                load_data ? max_value :
144                                pull_data ? (depth_q - DepthOne) :
145                                depth_q;
146                     
147        1/1              assign ptr_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
148                                pull_data ? (ptr_q + DepthOne) :
149                                ptr_q;
150                     
151        1/1              assign data_d = clear_data ? '0 :
           Tests:       T1 T2 T3 
152                                load_data ? wdata_i :
153                                data_q;
154                     
155                         // set outputs
156        1/1              assign wready_o = (depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
157        1/1              assign rdata_o =  rdata_shifted[OutW-1:0];
           Tests:       T1 T2 T3 
158        1/1              assign rvalid_o = !(depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
159                     
160                         // Avoid possible lint errors in case InW > OutW.
161                         if (InW > OutW) begin : gen_unused
162                           logic [MaxW-MinW-1:0] unused_rdata_shifted;
163        1/1                assign unused_rdata_shifted = rdata_shifted[MaxW-1:MinW];
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep
TotalCoveredPercent
Conditions424095.24
Logical424095.24
Non-Logical00
Event00

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3 

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable 

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3 

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT23,T54,T176
11CoveredT1,T2,T3 

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep
Line No.TotalCoveredPercent
Branches 14 14 100.00
TERNARY 142 4 4 100.00
TERNARY 147 3 3 100.00
TERNARY 151 3 3 100.00
IF 82 2 2 100.00
IF 127 2 2 100.00 



142            assign depth_d =  clear_status ? '0 :
                                              -1-  
                                              ==>  
143                   load_data ? max_value :
                                -2-  
                                ==>  
144                   pull_data ? (depth_q - DepthOne) :
                                -3-  
                                ==>  
                                ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3 



147            assign ptr_d =  clear_status ? '0 :
                                            -1-  
                                            ==>  
148                   pull_data ? (ptr_q + DepthOne) :
                                -2-  
                                ==>  
                                ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



151            assign data_d = clear_data ? '0 :
                                          -1-  
                                          ==>  
152                   load_data ? wdata_i :
                                -2-  
                                ==>  
                                ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



82             if (!rst_ni) begin
               -1-  
83               depth_q <= '0;
                 ==>
84               data_q  <= '0;
85               clr_q   <= 1'b1;
86             end else begin
87               depth_q <= depth_d;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



127              if (!rst_ni) begin
                 -1-  
128                ptr_q   <= '0;
                   ==>
129              end else begin
130                ptr_q   <= ptr_d;
                   ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataOStableWhenPending_A 10948233 7658891 0 933
ValidOPairedWithReadyI_A 10948233 7658891 0 0


DataOStableWhenPending_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10948233 7658891 0 933
T1 1112 883 0 1
T2 1001 740 0 1
T3 1400 797 0 1
T4 2011 987 0 1
T5 1303 0 0 1
T6 15518 8644 0 1
T9 2762 0 0 1
T22 750 0 0 1
T23 1742 1062 0 1
T24 1221 0 0 1
T25 0 1183 0 0
T26 0 2743 0 0
T28 0 861 0 0
T71 0 1235 0 0

ValidOPairedWithReadyI_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10948233 7658891 0 0
T1 1112 883 0 0
T2 1001 740 0 0
T3 1400 797 0 0
T4 2011 987 0 0
T5 1303 0 0 0
T6 15518 8644 0 0
T9 2762 0 0 0
T22 750 0 0 0
T23 1742 1062 0 0
T24 1221 0 0 0
T25 0 1183 0 0
T26 0 2743 0 0
T28 0 861 0 0
T71 0 1235 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep
Line No.TotalCoveredPercent
TOTAL2424100.00
ALWAYS8277100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9611100.00
ALWAYS12733100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN16311100.00


81                        always_ff @(posedge clk_i or negedge rst_ni) begin
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                depth_q <= '0;
           Tests:       T1 T2 T3 
84         1/1                data_q  <= '0;
           Tests:       T1 T2 T3 
85         1/1                clr_q   <= 1'b1;
           Tests:       T1 T2 T3 
86                          end else begin
87         1/1                depth_q <= depth_d;
           Tests:       T1 T2 T3 
88         1/1                data_q  <= data_d;
           Tests:       T1 T2 T3 
89         1/1                clr_q   <= clr_d;
           Tests:       T1 T2 T3 
90                          end
91                        end
92                      
93                        // flop for handling reset case for clr
94         1/1            assign clr_d = clr_i;
           Tests:       T1 T2 T3 
95                      
96         1/1            assign depth_o = depth_q;
           Tests:       T1 T2 T3 
97                      
98                        if (InW < OutW) begin : gen_pack_mode
99                          logic [MaxW-1:0] wdata_shifted;
100                     
101                         assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW);
102                         assign clear_status = (rready_i && rvalid_o) || clr_q;
103                         assign clear_data = (ClearOnRead && clear_status) || clr_q;
104                         assign load_data = wvalid_i && wready_o;
105                     
106                         assign depth_d =  clear_status ? '0 :
107                                load_data ? (depth_q + DepthOne):
108                                depth_q;
109                     
110                         assign data_d = clear_data ? '0 :
111                                load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) :
112                                data_q;
113                     
114                         // set outputs
115                         assign wready_o = !(depth_q == FullDepth) && !clr_q;
116                         assign rdata_o =  data_q;
117                         assign rvalid_o = (depth_q == FullDepth) && !clr_q;
118                     
119                       end else begin : gen_unpack_mode
120                         logic [MaxW-1:0] rdata_shifted;
121                         logic            pull_data;
122                         logic [DepthW:0] ptr_q, ptr_d;
123                         logic [DepthW:0] lsb_is_one;
124                         logic [DepthW:0] max_value;
125                     
126                         always_ff @(posedge clk_i or negedge rst_ni) begin
127        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
128        1/1                  ptr_q   <= '0;
           Tests:       T1 T2 T3 
129                           end else begin
130        1/1                  ptr_q   <= ptr_d;
           Tests:       T1 T2 T3 
131                           end
132                         end
133                     
134                         assign lsb_is_one = {{DepthW{1'b0}},1'b1};
135                         assign max_value = FullDepth;
136        1/1              assign rdata_shifted = data_q >> ptr_q*OutW;
           Tests:       T1 T2 T3 
137        1/1              assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q;
           Tests:       T1 T2 T3 
138        1/1              assign clear_data = (ClearOnRead && clear_status) || clr_q;
           Tests:       T1 T2 T3 
139        1/1              assign load_data = wvalid_i && wready_o;
           Tests:       T1 T2 T3 
140        1/1              assign pull_data = rvalid_o && rready_i;
           Tests:       T1 T2 T3 
141                     
142        1/1              assign depth_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
143                                load_data ? max_value :
144                                pull_data ? (depth_q - DepthOne) :
145                                depth_q;
146                     
147        1/1              assign ptr_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
148                                pull_data ? (ptr_q + DepthOne) :
149                                ptr_q;
150                     
151        1/1              assign data_d = clear_data ? '0 :
           Tests:       T1 T2 T3 
152                                load_data ? wdata_i :
153                                data_q;
154                     
155                         // set outputs
156        1/1              assign wready_o = (depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
157        1/1              assign rdata_o =  rdata_shifted[OutW-1:0];
           Tests:       T1 T2 T3 
158        1/1              assign rvalid_o = !(depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
159                     
160                         // Avoid possible lint errors in case InW > OutW.
161                         if (InW > OutW) begin : gen_unused
162                           logic [MaxW-MinW-1:0] unused_rdata_shifted;
163        1/1                assign unused_rdata_shifted = rdata_shifted[MaxW-1:MinW];
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep
TotalCoveredPercent
Conditions424095.24
Logical424095.24
Non-Logical00
Event00

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT14,T39,T47 

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------
-1--2-StatusTests
01CoveredT14,T39,T47
10CoveredT14,T39,T40
11CoveredT14,T39,T47 

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT14,T39,T47 

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable 

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT14,T39,T40 

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT14,T39,T40
11CoveredT14,T39,T40 

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT14,T39,T40 

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT14,T39,T40 

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT14,T39,T40 

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT14,T39,T40 

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----
-1--2-StatusTests
01CoveredT14,T39,T40
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT76,T231,T232
11CoveredT14,T39,T40 

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------
-1-StatusTests
0CoveredT14,T39,T40
1CoveredT1,T2,T3 

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep
Line No.TotalCoveredPercent
Branches 14 14 100.00
TERNARY 142 4 4 100.00
TERNARY 147 3 3 100.00
TERNARY 151 3 3 100.00
IF 82 2 2 100.00
IF 127 2 2 100.00 



142            assign depth_d =  clear_status ? '0 :
                                              -1-  
                                              ==>  
143                   load_data ? max_value :
                                -2-  
                                ==>  
144                   pull_data ? (depth_q - DepthOne) :
                                -3-  
                                ==>  
                                ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T14,T39,T40
0 0 1 Covered T14,T39,T40
0 0 0 Covered T1,T2,T3 



147            assign ptr_d =  clear_status ? '0 :
                                            -1-  
                                            ==>  
148                   pull_data ? (ptr_q + DepthOne) :
                                -2-  
                                ==>  
                                ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T14,T39,T40
0 0 Covered T1,T2,T3 



151            assign data_d = clear_data ? '0 :
                                          -1-  
                                          ==>  
152                   load_data ? wdata_i :
                                -2-  
                                ==>  
                                ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T14,T39,T40
0 0 Covered T1,T2,T3 



82             if (!rst_ni) begin
               -1-  
83               depth_q <= '0;
                 ==>
84               data_q  <= '0;
85               clr_q   <= 1'b1;
86             end else begin
87               depth_q <= depth_d;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



127              if (!rst_ni) begin
                 -1-  
128                ptr_q   <= '0;
                   ==>
129              end else begin
130                ptr_q   <= ptr_d;
                   ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataOStableWhenPending_A 10948233 252068 0 933
ValidOPairedWithReadyI_A 10948233 252068 0 0


DataOStableWhenPending_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10948233 252068 0 933
T11 4152 0 0 1
T14 3457 938 0 1
T19 2271 0 0 1
T27 2501 0 0 1
T29 1255 0 0 1
T39 0 1174 0 0
T40 0 360 0 0
T41 0 879 0 0
T42 0 1420 0 0
T46 915 0 0 1
T47 0 2561 0 0
T67 1209 0 0 1
T68 1864 0 0 1
T69 1103 0 0 1
T72 1876 0 0 1
T74 0 1131 0 0
T75 0 1073 0 0
T76 0 136 0 0
T77 0 5089 0 0

ValidOPairedWithReadyI_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10948233 252068 0 0
T11 4152 0 0 0
T14 3457 938 0 0
T19 2271 0 0 0
T27 2501 0 0 0
T29 1255 0 0 0
T39 0 1174 0 0
T40 0 360 0 0
T41 0 879 0 0
T42 0 1420 0 0
T46 915 0 0 0
T47 0 2561 0 0
T67 1209 0 0 0
T68 1864 0 0 0
T69 1103 0 0 0
T72 1876 0 0 0
T74 0 1131 0 0
T75 0 1073 0 0
T76 0 136 0 0
T77 0 5089 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep
Line No.TotalCoveredPercent
TOTAL2424100.00
ALWAYS8277100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9611100.00
ALWAYS12733100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN16311100.00


81                        always_ff @(posedge clk_i or negedge rst_ni) begin
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                depth_q <= '0;
           Tests:       T1 T2 T3 
84         1/1                data_q  <= '0;
           Tests:       T1 T2 T3 
85         1/1                clr_q   <= 1'b1;
           Tests:       T1 T2 T3 
86                          end else begin
87         1/1                depth_q <= depth_d;
           Tests:       T1 T2 T3 
88         1/1                data_q  <= data_d;
           Tests:       T1 T2 T3 
89         1/1                clr_q   <= clr_d;
           Tests:       T1 T2 T3 
90                          end
91                        end
92                      
93                        // flop for handling reset case for clr
94         1/1            assign clr_d = clr_i;
           Tests:       T1 T2 T3 
95                      
96         1/1            assign depth_o = depth_q;
           Tests:       T1 T2 T3 
97                      
98                        if (InW < OutW) begin : gen_pack_mode
99                          logic [MaxW-1:0] wdata_shifted;
100                     
101                         assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW);
102                         assign clear_status = (rready_i && rvalid_o) || clr_q;
103                         assign clear_data = (ClearOnRead && clear_status) || clr_q;
104                         assign load_data = wvalid_i && wready_o;
105                     
106                         assign depth_d =  clear_status ? '0 :
107                                load_data ? (depth_q + DepthOne):
108                                depth_q;
109                     
110                         assign data_d = clear_data ? '0 :
111                                load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) :
112                                data_q;
113                     
114                         // set outputs
115                         assign wready_o = !(depth_q == FullDepth) && !clr_q;
116                         assign rdata_o =  data_q;
117                         assign rvalid_o = (depth_q == FullDepth) && !clr_q;
118                     
119                       end else begin : gen_unpack_mode
120                         logic [MaxW-1:0] rdata_shifted;
121                         logic            pull_data;
122                         logic [DepthW:0] ptr_q, ptr_d;
123                         logic [DepthW:0] lsb_is_one;
124                         logic [DepthW:0] max_value;
125                     
126                         always_ff @(posedge clk_i or negedge rst_ni) begin
127        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
128        1/1                  ptr_q   <= '0;
           Tests:       T1 T2 T3 
129                           end else begin
130        1/1                  ptr_q   <= ptr_d;
           Tests:       T1 T2 T3 
131                           end
132                         end
133                     
134                         assign lsb_is_one = {{DepthW{1'b0}},1'b1};
135                         assign max_value = FullDepth;
136        1/1              assign rdata_shifted = data_q >> ptr_q*OutW;
           Tests:       T1 T2 T3 
137        1/1              assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q;
           Tests:       T1 T2 T3 
138        1/1              assign clear_data = (ClearOnRead && clear_status) || clr_q;
           Tests:       T1 T2 T3 
139        1/1              assign load_data = wvalid_i && wready_o;
           Tests:       T1 T2 T3 
140        1/1              assign pull_data = rvalid_o && rready_i;
           Tests:       T1 T2 T3 
141                     
142        1/1              assign depth_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
143                                load_data ? max_value :
144                                pull_data ? (depth_q - DepthOne) :
145                                depth_q;
146                     
147        1/1              assign ptr_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
148                                pull_data ? (ptr_q + DepthOne) :
149                                ptr_q;
150                     
151        1/1              assign data_d = clear_data ? '0 :
           Tests:       T1 T2 T3 
152                                load_data ? wdata_i :
153                                data_q;
154                     
155                         // set outputs
156        1/1              assign wready_o = (depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
157        1/1              assign rdata_o =  rdata_shifted[OutW-1:0];
           Tests:       T1 T2 T3 
158        1/1              assign rvalid_o = !(depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
159                     
160                         // Avoid possible lint errors in case InW > OutW.
161                         if (InW > OutW) begin : gen_unused
162                           logic [MaxW-MinW-1:0] unused_rdata_shifted;
163        1/1                assign unused_rdata_shifted = rdata_shifted[MaxW-1:MinW];
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep
TotalCoveredPercent
Conditions424095.24
Logical424095.24
Non-Logical00
Event00

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT26,T38,T43 

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------
-1--2-StatusTests
01CoveredT26,T38,T43
10CoveredT26,T38,T46
11CoveredT26,T38,T43 

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT26,T38,T43 

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable 

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT26,T38,T46 

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT26,T38,T46
11CoveredT26,T38,T46 

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT26,T38,T46 

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT26,T38,T46 

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT26,T38,T46 

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT26,T38,T46 

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----
-1--2-StatusTests
01CoveredT26,T38,T46
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT46,T233,T224
11CoveredT26,T38,T46 

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------
-1-StatusTests
0CoveredT26,T38,T46
1CoveredT1,T2,T3 

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep
Line No.TotalCoveredPercent
Branches 14 14 100.00
TERNARY 142 4 4 100.00
TERNARY 147 3 3 100.00
TERNARY 151 3 3 100.00
IF 82 2 2 100.00
IF 127 2 2 100.00 



142            assign depth_d =  clear_status ? '0 :
                                              -1-  
                                              ==>  
143                   load_data ? max_value :
                                -2-  
                                ==>  
144                   pull_data ? (depth_q - DepthOne) :
                                -3-  
                                ==>  
                                ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T26,T38,T46
0 0 1 Covered T26,T38,T46
0 0 0 Covered T1,T2,T3 



147            assign ptr_d =  clear_status ? '0 :
                                            -1-  
                                            ==>  
148                   pull_data ? (ptr_q + DepthOne) :
                                -2-  
                                ==>  
                                ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T26,T38,T46
0 0 Covered T1,T2,T3 



151            assign data_d = clear_data ? '0 :
                                          -1-  
                                          ==>  
152                   load_data ? wdata_i :
                                -2-  
                                ==>  
                                ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T26,T38,T46
0 0 Covered T1,T2,T3 



82             if (!rst_ni) begin
               -1-  
83               depth_q <= '0;
                 ==>
84               data_q  <= '0;
85               clr_q   <= 1'b1;
86             end else begin
87               depth_q <= depth_d;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



127              if (!rst_ni) begin
                 -1-  
128                ptr_q   <= '0;
                   ==>
129              end else begin
130                ptr_q   <= ptr_d;
                   ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataOStableWhenPending_A 10948233 259605 0 933
ValidOPairedWithReadyI_A 10948233 259605 0 0


DataOStableWhenPending_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10948233 259605 0 933
T10 1703 0 0 1
T14 3457 0 0 1
T15 22637 0 0 1
T17 1885 0 0 1
T26 4529 4383 0 1
T28 1808 0 0 1
T38 1236 996 0 1
T43 0 1033 0 0
T44 0 2263 0 0
T45 0 1071 0 0
T46 0 732 0 0
T47 0 1952 0 0
T57 0 1398 0 0
T67 1209 0 0 1
T68 1864 0 0 1
T69 1103 0 0 1
T82 0 1401 0 0
T83 0 754 0 0

ValidOPairedWithReadyI_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10948233 259605 0 0
T10 1703 0 0 0
T14 3457 0 0 0
T15 22637 0 0 0
T17 1885 0 0 0
T26 4529 4383 0 0
T28 1808 0 0 0
T38 1236 996 0 0
T43 0 1033 0 0
T44 0 2263 0 0
T45 0 1071 0 0
T46 0 732 0 0
T47 0 1952 0 0
T57 0 1398 0 0
T67 1209 0 0 0
T68 1864 0 0 0
T69 1103 0 0 0
T82 0 1401 0 0
T83 0 754 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep
Line No.TotalCoveredPercent
TOTAL2424100.00
ALWAYS8277100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9611100.00
ALWAYS12733100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN16311100.00


81                        always_ff @(posedge clk_i or negedge rst_ni) begin
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                depth_q <= '0;
           Tests:       T1 T2 T3 
84         1/1                data_q  <= '0;
           Tests:       T1 T2 T3 
85         1/1                clr_q   <= 1'b1;
           Tests:       T1 T2 T3 
86                          end else begin
87         1/1                depth_q <= depth_d;
           Tests:       T1 T2 T3 
88         1/1                data_q  <= data_d;
           Tests:       T1 T2 T3 
89         1/1                clr_q   <= clr_d;
           Tests:       T1 T2 T3 
90                          end
91                        end
92                      
93                        // flop for handling reset case for clr
94         1/1            assign clr_d = clr_i;
           Tests:       T1 T2 T3 
95                      
96         1/1            assign depth_o = depth_q;
           Tests:       T1 T2 T3 
97                      
98                        if (InW < OutW) begin : gen_pack_mode
99                          logic [MaxW-1:0] wdata_shifted;
100                     
101                         assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW);
102                         assign clear_status = (rready_i && rvalid_o) || clr_q;
103                         assign clear_data = (ClearOnRead && clear_status) || clr_q;
104                         assign load_data = wvalid_i && wready_o;
105                     
106                         assign depth_d =  clear_status ? '0 :
107                                load_data ? (depth_q + DepthOne):
108                                depth_q;
109                     
110                         assign data_d = clear_data ? '0 :
111                                load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) :
112                                data_q;
113                     
114                         // set outputs
115                         assign wready_o = !(depth_q == FullDepth) && !clr_q;
116                         assign rdata_o =  data_q;
117                         assign rvalid_o = (depth_q == FullDepth) && !clr_q;
118                     
119                       end else begin : gen_unpack_mode
120                         logic [MaxW-1:0] rdata_shifted;
121                         logic            pull_data;
122                         logic [DepthW:0] ptr_q, ptr_d;
123                         logic [DepthW:0] lsb_is_one;
124                         logic [DepthW:0] max_value;
125                     
126                         always_ff @(posedge clk_i or negedge rst_ni) begin
127        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
128        1/1                  ptr_q   <= '0;
           Tests:       T1 T2 T3 
129                           end else begin
130        1/1                  ptr_q   <= ptr_d;
           Tests:       T1 T2 T3 
131                           end
132                         end
133                     
134                         assign lsb_is_one = {{DepthW{1'b0}},1'b1};
135                         assign max_value = FullDepth;
136        1/1              assign rdata_shifted = data_q >> ptr_q*OutW;
           Tests:       T1 T2 T3 
137        1/1              assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q;
           Tests:       T1 T2 T3 
138        1/1              assign clear_data = (ClearOnRead && clear_status) || clr_q;
           Tests:       T1 T2 T3 
139        1/1              assign load_data = wvalid_i && wready_o;
           Tests:       T1 T2 T3 
140        1/1              assign pull_data = rvalid_o && rready_i;
           Tests:       T1 T2 T3 
141                     
142        1/1              assign depth_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
143                                load_data ? max_value :
144                                pull_data ? (depth_q - DepthOne) :
145                                depth_q;
146                     
147        1/1              assign ptr_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
148                                pull_data ? (ptr_q + DepthOne) :
149                                ptr_q;
150                     
151        1/1              assign data_d = clear_data ? '0 :
           Tests:       T1 T2 T3 
152                                load_data ? wdata_i :
153                                data_q;
154                     
155                         // set outputs
156        1/1              assign wready_o = (depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
157        1/1              assign rdata_o =  rdata_shifted[OutW-1:0];
           Tests:       T1 T2 T3 
158        1/1              assign rvalid_o = !(depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
159                     
160                         // Avoid possible lint errors in case InW > OutW.
161                         if (InW > OutW) begin : gen_unused
162                           logic [MaxW-MinW-1:0] unused_rdata_shifted;
163        1/1                assign unused_rdata_shifted = rdata_shifted[MaxW-1:MinW];
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep
TotalCoveredPercent
Conditions424095.24
Logical424095.24
Non-Logical00
Event00

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT9,T44,T49 

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------
-1--2-StatusTests
01CoveredT9,T44,T49
10CoveredT9,T44,T49
11CoveredT9,T44,T49 

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T44,T49 

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable 

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT9,T7,T44 

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT9,T7,T44
11CoveredT9,T44,T49 

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T7,T44 

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T44,T49 

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T44,T49 

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T7,T44 

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----
-1--2-StatusTests
01CoveredT9,T7,T44
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT50,T177,T234
11CoveredT9,T7,T44 

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------
-1-StatusTests
0CoveredT9,T7,T44
1CoveredT1,T2,T3 

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep
Line No.TotalCoveredPercent
Branches 14 14 100.00
TERNARY 142 4 4 100.00
TERNARY 147 3 3 100.00
TERNARY 151 3 3 100.00
IF 82 2 2 100.00
IF 127 2 2 100.00 



142            assign depth_d =  clear_status ? '0 :
                                              -1-  
                                              ==>  
143                   load_data ? max_value :
                                -2-  
                                ==>  
144                   pull_data ? (depth_q - DepthOne) :
                                -3-  
                                ==>  
                                ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T9,T7,T44
0 0 1 Covered T9,T44,T49
0 0 0 Covered T1,T2,T3 



147            assign ptr_d =  clear_status ? '0 :
                                            -1-  
                                            ==>  
148                   pull_data ? (ptr_q + DepthOne) :
                                -2-  
                                ==>  
                                ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T9,T44,T49
0 0 Covered T1,T2,T3 



151            assign data_d = clear_data ? '0 :
                                          -1-  
                                          ==>  
152                   load_data ? wdata_i :
                                -2-  
                                ==>  
                                ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T9,T7,T44
0 0 Covered T1,T2,T3 



82             if (!rst_ni) begin
               -1-  
83               depth_q <= '0;
                 ==>
84               data_q  <= '0;
85               clr_q   <= 1'b1;
86             end else begin
87               depth_q <= depth_d;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



127              if (!rst_ni) begin
                 -1-  
128                ptr_q   <= '0;
                   ==>
129              end else begin
130                ptr_q   <= ptr_d;
                   ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataOStableWhenPending_A 10948233 206857 0 933
ValidOPairedWithReadyI_A 10948233 206857 0 0


DataOStableWhenPending_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10948233 206857 0 933
T7 0 580 0 0
T9 2762 1144 0 1
T10 1703 0 0 1
T12 0 1210 0 0
T15 22637 0 0 1
T17 1885 0 0 1
T25 1633 0 0 1
T26 4529 0 0 1
T28 1808 0 0 1
T44 0 2294 0 0
T47 0 2095 0 0
T49 0 1984 0 0
T50 0 667 0 0
T59 1637 0 0 1
T60 4196 0 0 1
T71 1482 0 0 1
T78 0 1854 0 0
T85 0 575 0 0
T86 0 781 0 0

ValidOPairedWithReadyI_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10948233 206857 0 0
T7 0 580 0 0
T9 2762 1144 0 0
T10 1703 0 0 0
T12 0 1210 0 0
T15 22637 0 0 0
T17 1885 0 0 0
T25 1633 0 0 0
T26 4529 0 0 0
T28 1808 0 0 0
T44 0 2294 0 0
T47 0 2095 0 0
T49 0 1984 0 0
T50 0 667 0 0
T59 1637 0 0 0
T60 4196 0 0 0
T71 1482 0 0 0
T78 0 1854 0 0
T85 0 575 0 0
T86 0 781 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep
Line No.TotalCoveredPercent
TOTAL2424100.00
ALWAYS8277100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9611100.00
ALWAYS12733100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN16311100.00


81                        always_ff @(posedge clk_i or negedge rst_ni) begin
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                depth_q <= '0;
           Tests:       T1 T2 T3 
84         1/1                data_q  <= '0;
           Tests:       T1 T2 T3 
85         1/1                clr_q   <= 1'b1;
           Tests:       T1 T2 T3 
86                          end else begin
87         1/1                depth_q <= depth_d;
           Tests:       T1 T2 T3 
88         1/1                data_q  <= data_d;
           Tests:       T1 T2 T3 
89         1/1                clr_q   <= clr_d;
           Tests:       T1 T2 T3 
90                          end
91                        end
92                      
93                        // flop for handling reset case for clr
94         1/1            assign clr_d = clr_i;
           Tests:       T1 T2 T3 
95                      
96         1/1            assign depth_o = depth_q;
           Tests:       T1 T2 T3 
97                      
98                        if (InW < OutW) begin : gen_pack_mode
99                          logic [MaxW-1:0] wdata_shifted;
100                     
101                         assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW);
102                         assign clear_status = (rready_i && rvalid_o) || clr_q;
103                         assign clear_data = (ClearOnRead && clear_status) || clr_q;
104                         assign load_data = wvalid_i && wready_o;
105                     
106                         assign depth_d =  clear_status ? '0 :
107                                load_data ? (depth_q + DepthOne):
108                                depth_q;
109                     
110                         assign data_d = clear_data ? '0 :
111                                load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) :
112                                data_q;
113                     
114                         // set outputs
115                         assign wready_o = !(depth_q == FullDepth) && !clr_q;
116                         assign rdata_o =  data_q;
117                         assign rvalid_o = (depth_q == FullDepth) && !clr_q;
118                     
119                       end else begin : gen_unpack_mode
120                         logic [MaxW-1:0] rdata_shifted;
121                         logic            pull_data;
122                         logic [DepthW:0] ptr_q, ptr_d;
123                         logic [DepthW:0] lsb_is_one;
124                         logic [DepthW:0] max_value;
125                     
126                         always_ff @(posedge clk_i or negedge rst_ni) begin
127        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
128        1/1                  ptr_q   <= '0;
           Tests:       T1 T2 T3 
129                           end else begin
130        1/1                  ptr_q   <= ptr_d;
           Tests:       T1 T2 T3 
131                           end
132                         end
133                     
134                         assign lsb_is_one = {{DepthW{1'b0}},1'b1};
135                         assign max_value = FullDepth;
136        1/1              assign rdata_shifted = data_q >> ptr_q*OutW;
           Tests:       T1 T2 T3 
137        1/1              assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q;
           Tests:       T1 T2 T3 
138        1/1              assign clear_data = (ClearOnRead && clear_status) || clr_q;
           Tests:       T1 T2 T3 
139        1/1              assign load_data = wvalid_i && wready_o;
           Tests:       T1 T2 T3 
140        1/1              assign pull_data = rvalid_o && rready_i;
           Tests:       T1 T2 T3 
141                     
142        1/1              assign depth_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
143                                load_data ? max_value :
144                                pull_data ? (depth_q - DepthOne) :
145                                depth_q;
146                     
147        1/1              assign ptr_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
148                                pull_data ? (ptr_q + DepthOne) :
149                                ptr_q;
150                     
151        1/1              assign data_d = clear_data ? '0 :
           Tests:       T1 T2 T3 
152                                load_data ? wdata_i :
153                                data_q;
154                     
155                         // set outputs
156        1/1              assign wready_o = (depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
157        1/1              assign rdata_o =  rdata_shifted[OutW-1:0];
           Tests:       T1 T2 T3 
158        1/1              assign rvalid_o = !(depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
159                     
160                         // Avoid possible lint errors in case InW > OutW.
161                         if (InW > OutW) begin : gen_unused
162                           logic [MaxW-MinW-1:0] unused_rdata_shifted;
163        1/1                assign unused_rdata_shifted = rdata_shifted[MaxW-1:MinW];
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep
TotalCoveredPercent
Conditions424095.24
Logical424095.24
Non-Logical00
Event00

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT19,T39,T51 

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------
-1--2-StatusTests
01CoveredT19,T39,T51
10CoveredT19,T39,T51
11CoveredT19,T39,T51 

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT19,T39,T51 

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable 

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT19,T39,T51 

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT19,T39,T51
11CoveredT19,T39,T51 

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT19,T39,T51 

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT19,T39,T51 

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT19,T39,T51 

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT19,T39,T51 

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----
-1--2-StatusTests
01CoveredT19,T39,T51
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT51,T235,T236
11CoveredT19,T39,T51 

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------
-1-StatusTests
0CoveredT19,T39,T51
1CoveredT1,T2,T3 

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep
Line No.TotalCoveredPercent
Branches 14 14 100.00
TERNARY 142 4 4 100.00
TERNARY 147 3 3 100.00
TERNARY 151 3 3 100.00
IF 82 2 2 100.00
IF 127 2 2 100.00 



142            assign depth_d =  clear_status ? '0 :
                                              -1-  
                                              ==>  
143                   load_data ? max_value :
                                -2-  
                                ==>  
144                   pull_data ? (depth_q - DepthOne) :
                                -3-  
                                ==>  
                                ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T19,T39,T51
0 0 1 Covered T19,T39,T51
0 0 0 Covered T1,T2,T3 



147            assign ptr_d =  clear_status ? '0 :
                                            -1-  
                                            ==>  
148                   pull_data ? (ptr_q + DepthOne) :
                                -2-  
                                ==>  
                                ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T19,T39,T51
0 0 Covered T1,T2,T3 



151            assign data_d = clear_data ? '0 :
                                          -1-  
                                          ==>  
152                   load_data ? wdata_i :
                                -2-  
                                ==>  
                                ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T19,T39,T51
0 0 Covered T1,T2,T3 



82             if (!rst_ni) begin
               -1-  
83               depth_q <= '0;
                 ==>
84               data_q  <= '0;
85               clr_q   <= 1'b1;
86             end else begin
87               depth_q <= depth_d;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



127              if (!rst_ni) begin
                 -1-  
128                ptr_q   <= '0;
                   ==>
129              end else begin
130                ptr_q   <= ptr_d;
                   ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataOStableWhenPending_A 10948233 191197 0 933
ValidOPairedWithReadyI_A 10948233 191197 0 0


DataOStableWhenPending_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10948233 191197 0 933
T16 25267 0 0 1
T19 2271 1135 0 1
T20 0 1009 0 0
T27 2501 0 0 1
T39 1740 1137 0 1
T44 0 2282 0 0
T46 915 0 0 1
T47 0 1962 0 0
T49 0 1247 0 0
T51 0 71 0 0
T61 26364 0 0 1
T70 1158 0 0 1
T72 1876 0 0 1
T89 0 819 0 0
T90 0 1096 0 0
T91 0 1093 0 0
T92 776 0 0 1
T93 1265 0 0 1

ValidOPairedWithReadyI_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10948233 191197 0 0
T16 25267 0 0 0
T19 2271 1135 0 0
T20 0 1009 0 0
T27 2501 0 0 0
T39 1740 1137 0 0
T44 0 2282 0 0
T46 915 0 0 0
T47 0 1962 0 0
T49 0 1247 0 0
T51 0 71 0 0
T61 26364 0 0 0
T70 1158 0 0 0
T72 1876 0 0 0
T89 0 819 0 0
T90 0 1096 0 0
T91 0 1093 0 0
T92 776 0 0 0
T93 1265 0 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep
Line No.TotalCoveredPercent
TOTAL2424100.00
ALWAYS8277100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9611100.00
ALWAYS12733100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN16311100.00


81                        always_ff @(posedge clk_i or negedge rst_ni) begin
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                depth_q <= '0;
           Tests:       T1 T2 T3 
84         1/1                data_q  <= '0;
           Tests:       T1 T2 T3 
85         1/1                clr_q   <= 1'b1;
           Tests:       T1 T2 T3 
86                          end else begin
87         1/1                depth_q <= depth_d;
           Tests:       T1 T2 T3 
88         1/1                data_q  <= data_d;
           Tests:       T1 T2 T3 
89         1/1                clr_q   <= clr_d;
           Tests:       T1 T2 T3 
90                          end
91                        end
92                      
93                        // flop for handling reset case for clr
94         1/1            assign clr_d = clr_i;
           Tests:       T1 T2 T3 
95                      
96         1/1            assign depth_o = depth_q;
           Tests:       T1 T2 T3 
97                      
98                        if (InW < OutW) begin : gen_pack_mode
99                          logic [MaxW-1:0] wdata_shifted;
100                     
101                         assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW);
102                         assign clear_status = (rready_i && rvalid_o) || clr_q;
103                         assign clear_data = (ClearOnRead && clear_status) || clr_q;
104                         assign load_data = wvalid_i && wready_o;
105                     
106                         assign depth_d =  clear_status ? '0 :
107                                load_data ? (depth_q + DepthOne):
108                                depth_q;
109                     
110                         assign data_d = clear_data ? '0 :
111                                load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) :
112                                data_q;
113                     
114                         // set outputs
115                         assign wready_o = !(depth_q == FullDepth) && !clr_q;
116                         assign rdata_o =  data_q;
117                         assign rvalid_o = (depth_q == FullDepth) && !clr_q;
118                     
119                       end else begin : gen_unpack_mode
120                         logic [MaxW-1:0] rdata_shifted;
121                         logic            pull_data;
122                         logic [DepthW:0] ptr_q, ptr_d;
123                         logic [DepthW:0] lsb_is_one;
124                         logic [DepthW:0] max_value;
125                     
126                         always_ff @(posedge clk_i or negedge rst_ni) begin
127        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
128        1/1                  ptr_q   <= '0;
           Tests:       T1 T2 T3 
129                           end else begin
130        1/1                  ptr_q   <= ptr_d;
           Tests:       T1 T2 T3 
131                           end
132                         end
133                     
134                         assign lsb_is_one = {{DepthW{1'b0}},1'b1};
135                         assign max_value = FullDepth;
136        1/1              assign rdata_shifted = data_q >> ptr_q*OutW;
           Tests:       T1 T2 T3 
137        1/1              assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q;
           Tests:       T1 T2 T3 
138        1/1              assign clear_data = (ClearOnRead && clear_status) || clr_q;
           Tests:       T1 T2 T3 
139        1/1              assign load_data = wvalid_i && wready_o;
           Tests:       T1 T2 T3 
140        1/1              assign pull_data = rvalid_o && rready_i;
           Tests:       T1 T2 T3 
141                     
142        1/1              assign depth_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
143                                load_data ? max_value :
144                                pull_data ? (depth_q - DepthOne) :
145                                depth_q;
146                     
147        1/1              assign ptr_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
148                                pull_data ? (ptr_q + DepthOne) :
149                                ptr_q;
150                     
151        1/1              assign data_d = clear_data ? '0 :
           Tests:       T1 T2 T3 
152                                load_data ? wdata_i :
153                                data_q;
154                     
155                         // set outputs
156        1/1              assign wready_o = (depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
157        1/1              assign rdata_o =  rdata_shifted[OutW-1:0];
           Tests:       T1 T2 T3 
158        1/1              assign rvalid_o = !(depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
159                     
160                         // Avoid possible lint errors in case InW > OutW.
161                         if (InW > OutW) begin : gen_unused
162                           logic [MaxW-MinW-1:0] unused_rdata_shifted;
163        1/1                assign unused_rdata_shifted = rdata_shifted[MaxW-1:MinW];
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep
TotalCoveredPercent
Conditions424095.24
Logical424095.24
Non-Logical00
Event00

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT24,T52,T44 

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------
-1--2-StatusTests
01CoveredT24,T52,T44
10CoveredT24,T43,T52
11CoveredT24,T52,T44 

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T52,T44 

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable 

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT24,T43,T52 

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT24,T43,T52
11CoveredT24,T43,T52 

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T43,T52 

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T43,T52 

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T43,T52 

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT24,T43,T52 

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----
-1--2-StatusTests
01CoveredT24,T43,T52
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T98,T108
11CoveredT24,T43,T52 

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------
-1-StatusTests
0CoveredT24,T43,T52
1CoveredT1,T2,T3 

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep
Line No.TotalCoveredPercent
Branches 14 14 100.00
TERNARY 142 4 4 100.00
TERNARY 147 3 3 100.00
TERNARY 151 3 3 100.00
IF 82 2 2 100.00
IF 127 2 2 100.00 



142            assign depth_d =  clear_status ? '0 :
                                              -1-  
                                              ==>  
143                   load_data ? max_value :
                                -2-  
                                ==>  
144                   pull_data ? (depth_q - DepthOne) :
                                -3-  
                                ==>  
                                ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T24,T43,T52
0 0 1 Covered T24,T43,T52
0 0 0 Covered T1,T2,T3 



147            assign ptr_d =  clear_status ? '0 :
                                            -1-  
                                            ==>  
148                   pull_data ? (ptr_q + DepthOne) :
                                -2-  
                                ==>  
                                ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T24,T43,T52
0 0 Covered T1,T2,T3 



151            assign data_d = clear_data ? '0 :
                                          -1-  
                                          ==>  
152                   load_data ? wdata_i :
                                -2-  
                                ==>  
                                ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T24,T43,T52
0 0 Covered T1,T2,T3 



82             if (!rst_ni) begin
               -1-  
83               depth_q <= '0;
                 ==>
84               data_q  <= '0;
85               clr_q   <= 1'b1;
86             end else begin
87               depth_q <= depth_d;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



127              if (!rst_ni) begin
                 -1-  
128                ptr_q   <= '0;
                   ==>
129              end else begin
130                ptr_q   <= ptr_d;
                   ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataOStableWhenPending_A 10948233 162046 0 933
ValidOPairedWithReadyI_A 10948233 162046 0 0


DataOStableWhenPending_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10948233 162046 0 933
T9 2762 0 0 1
T10 1703 0 0 1
T17 1885 0 0 1
T24 1221 204 0 1
T25 1633 0 0 1
T26 4529 0 0 1
T28 1808 0 0 1
T33 0 435 0 0
T43 0 1077 0 0
T44 0 2188 0 0
T49 0 2253 0 0
T52 0 885 0 0
T59 1637 0 0 1
T60 4196 0 0 1
T71 1482 0 0 1
T86 0 717 0 0
T96 0 849 0 0
T97 0 650 0 0
T98 0 176 0 0

ValidOPairedWithReadyI_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10948233 162046 0 0
T9 2762 0 0 0
T10 1703 0 0 0
T17 1885 0 0 0
T24 1221 204 0 0
T25 1633 0 0 0
T26 4529 0 0 0
T28 1808 0 0 0
T33 0 435 0 0
T43 0 1077 0 0
T44 0 2188 0 0
T49 0 2253 0 0
T52 0 885 0 0
T59 1637 0 0 0
T60 4196 0 0 0
T71 1482 0 0 0
T86 0 717 0 0
T96 0 849 0 0
T97 0 650 0 0
T98 0 176 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep
Line No.TotalCoveredPercent
TOTAL2424100.00
ALWAYS8277100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9611100.00
ALWAYS12733100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN16311100.00


81                        always_ff @(posedge clk_i or negedge rst_ni) begin
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                depth_q <= '0;
           Tests:       T1 T2 T3 
84         1/1                data_q  <= '0;
           Tests:       T1 T2 T3 
85         1/1                clr_q   <= 1'b1;
           Tests:       T1 T2 T3 
86                          end else begin
87         1/1                depth_q <= depth_d;
           Tests:       T1 T2 T3 
88         1/1                data_q  <= data_d;
           Tests:       T1 T2 T3 
89         1/1                clr_q   <= clr_d;
           Tests:       T1 T2 T3 
90                          end
91                        end
92                      
93                        // flop for handling reset case for clr
94         1/1            assign clr_d = clr_i;
           Tests:       T1 T2 T3 
95                      
96         1/1            assign depth_o = depth_q;
           Tests:       T1 T2 T3 
97                      
98                        if (InW < OutW) begin : gen_pack_mode
99                          logic [MaxW-1:0] wdata_shifted;
100                     
101                         assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW);
102                         assign clear_status = (rready_i && rvalid_o) || clr_q;
103                         assign clear_data = (ClearOnRead && clear_status) || clr_q;
104                         assign load_data = wvalid_i && wready_o;
105                     
106                         assign depth_d =  clear_status ? '0 :
107                                load_data ? (depth_q + DepthOne):
108                                depth_q;
109                     
110                         assign data_d = clear_data ? '0 :
111                                load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) :
112                                data_q;
113                     
114                         // set outputs
115                         assign wready_o = !(depth_q == FullDepth) && !clr_q;
116                         assign rdata_o =  data_q;
117                         assign rvalid_o = (depth_q == FullDepth) && !clr_q;
118                     
119                       end else begin : gen_unpack_mode
120                         logic [MaxW-1:0] rdata_shifted;
121                         logic            pull_data;
122                         logic [DepthW:0] ptr_q, ptr_d;
123                         logic [DepthW:0] lsb_is_one;
124                         logic [DepthW:0] max_value;
125                     
126                         always_ff @(posedge clk_i or negedge rst_ni) begin
127        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
128        1/1                  ptr_q   <= '0;
           Tests:       T1 T2 T3 
129                           end else begin
130        1/1                  ptr_q   <= ptr_d;
           Tests:       T1 T2 T3 
131                           end
132                         end
133                     
134                         assign lsb_is_one = {{DepthW{1'b0}},1'b1};
135                         assign max_value = FullDepth;
136        1/1              assign rdata_shifted = data_q >> ptr_q*OutW;
           Tests:       T1 T2 T3 
137        1/1              assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q;
           Tests:       T1 T2 T3 
138        1/1              assign clear_data = (ClearOnRead && clear_status) || clr_q;
           Tests:       T1 T2 T3 
139        1/1              assign load_data = wvalid_i && wready_o;
           Tests:       T1 T2 T3 
140        1/1              assign pull_data = rvalid_o && rready_i;
           Tests:       T1 T2 T3 
141                     
142        1/1              assign depth_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
143                                load_data ? max_value :
144                                pull_data ? (depth_q - DepthOne) :
145                                depth_q;
146                     
147        1/1              assign ptr_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
148                                pull_data ? (ptr_q + DepthOne) :
149                                ptr_q;
150                     
151        1/1              assign data_d = clear_data ? '0 :
           Tests:       T1 T2 T3 
152                                load_data ? wdata_i :
153                                data_q;
154                     
155                         // set outputs
156        1/1              assign wready_o = (depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
157        1/1              assign rdata_o =  rdata_shifted[OutW-1:0];
           Tests:       T1 T2 T3 
158        1/1              assign rvalid_o = !(depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
159                     
160                         // Avoid possible lint errors in case InW > OutW.
161                         if (InW > OutW) begin : gen_unused
162                           logic [MaxW-MinW-1:0] unused_rdata_shifted;
163        1/1                assign unused_rdata_shifted = rdata_shifted[MaxW-1:MinW];
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep
TotalCoveredPercent
Conditions424095.24
Logical424095.24
Non-Logical00
Event00

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT26,T27,T54 

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------
-1--2-StatusTests
01CoveredT26,T27,T54
10CoveredT26,T27,T54
11CoveredT26,T27,T54 

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT26,T27,T54 

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable 

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT26,T27,T54 

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT26,T27,T54
11CoveredT26,T27,T54 

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT26,T27,T54 

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT26,T27,T54 

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT26,T27,T54 

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT26,T27,T54 

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----
-1--2-StatusTests
01CoveredT26,T27,T54
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT27,T55,T57
11CoveredT26,T27,T54 

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------
-1-StatusTests
0CoveredT26,T27,T54
1CoveredT1,T2,T3 

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep
Line No.TotalCoveredPercent
Branches 14 14 100.00
TERNARY 142 4 4 100.00
TERNARY 147 3 3 100.00
TERNARY 151 3 3 100.00
IF 82 2 2 100.00
IF 127 2 2 100.00 



142            assign depth_d =  clear_status ? '0 :
                                              -1-  
                                              ==>  
143                   load_data ? max_value :
                                -2-  
                                ==>  
144                   pull_data ? (depth_q - DepthOne) :
                                -3-  
                                ==>  
                                ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T26,T27,T54
0 0 1 Covered T26,T27,T54
0 0 0 Covered T1,T2,T3 



147            assign ptr_d =  clear_status ? '0 :
                                            -1-  
                                            ==>  
148                   pull_data ? (ptr_q + DepthOne) :
                                -2-  
                                ==>  
                                ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T26,T27,T54
0 0 Covered T1,T2,T3 



151            assign data_d = clear_data ? '0 :
                                          -1-  
                                          ==>  
152                   load_data ? wdata_i :
                                -2-  
                                ==>  
                                ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T26,T27,T54
0 0 Covered T1,T2,T3 



82             if (!rst_ni) begin
               -1-  
83               depth_q <= '0;
                 ==>
84               data_q  <= '0;
85               clr_q   <= 1'b1;
86             end else begin
87               depth_q <= depth_d;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



127              if (!rst_ni) begin
                 -1-  
128                ptr_q   <= '0;
                   ==>
129              end else begin
130                ptr_q   <= ptr_d;
                   ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataOStableWhenPending_A 10948233 168085 0 933
ValidOPairedWithReadyI_A 10948233 168085 0 0


DataOStableWhenPending_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10948233 168085 0 933
T10 1703 0 0 1
T14 3457 0 0 1
T15 22637 0 0 1
T17 1885 0 0 1
T26 4529 2724 0 1
T27 0 1592 0 0
T28 1808 0 0 1
T38 1236 0 0 1
T49 0 1259 0 0
T54 0 1307 0 0
T55 0 227 0 0
T57 0 130 0 0
T67 1209 0 0 1
T68 1864 0 0 1
T69 1103 0 0 1
T102 0 883 0 0
T103 0 776 0 0
T104 0 548 0 0
T105 0 867 0 0

ValidOPairedWithReadyI_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10948233 168085 0 0
T10 1703 0 0 0
T14 3457 0 0 0
T15 22637 0 0 0
T17 1885 0 0 0
T26 4529 2724 0 0
T27 0 1592 0 0
T28 1808 0 0 0
T38 1236 0 0 0
T49 0 1259 0 0
T54 0 1307 0 0
T55 0 227 0 0
T57 0 130 0 0
T67 1209 0 0 0
T68 1864 0 0 0
T69 1103 0 0 0
T102 0 883 0 0
T103 0 776 0 0
T104 0 548 0 0
T105 0 867 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%