ENTROPY_SRC Simulation Results

Monday May 15 2023 07:07:46 UTC

GitHub Revision: `3d5660d90`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 705130430

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	entropy_src_smoke	5.000s	34.064us	50	50	100.00
V1	csr_hw_reset	entropy_src_csr_hw_reset	4.000s	68.625us	5	5	100.00
V1	csr_rw	entropy_src_csr_rw	4.000s	65.404us	20	20	100.00
V1	csr_bit_bash	entropy_src_csr_bit_bash	14.000s	516.136us	5	5	100.00
V1	csr_aliasing	entropy_src_csr_aliasing	7.000s	146.551us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	entropy_src_csr_mem_rw_with_rand_reset	4.000s	30.874us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	entropy_src_csr_rw	4.000s	65.404us	20	20	100.00
		entropy_src_csr_aliasing	7.000s	146.551us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	entropy_src_smoke	5.000s	34.064us	50	50	100.00
		entropy_src_rng	11.017m	10.013ms	300	300	100.00
		entropy_src_fw_ov	2.017m	5.066ms	299	300	99.67
V2	firmware_mode	entropy_src_fw_ov	2.017m	5.066ms	299	300	99.67
V2	rng_mode	entropy_src_rng	11.017m	10.013ms	300	300	100.00
V2	rng_max_rate	entropy_src_rng_max_rate	10.950m	10.015ms	399	400	99.75
V2	health_checks	entropy_src_rng	11.017m	10.013ms	300	300	100.00
V2	conditioning	entropy_src_rng	11.017m	10.013ms	300	300	100.00
V2	interrupts	entropy_src_rng	11.017m	10.013ms	300	300	100.00
V2	alerts	entropy_src_rng	11.017m	10.013ms	300	300	100.00
		entropy_src_functional_alerts	5.000s	101.481us	50	50	100.00
V2	stress_all	entropy_src_stress_all	9.000s	2.562ms	50	50	100.00
V2	functional_errors	entropy_src_functional_errors	5.000s	196.360us	1000	1000	100.00
V2	intr_test	entropy_src_intr_test	4.000s	15.798us	50	50	100.00
V2	alert_test	entropy_src_alert_test	4.000s	37.035us	50	50	100.00
V2	tl_d_oob_addr_access	entropy_src_tl_errors	8.000s	271.062us	20	20	100.00
V2	tl_d_illegal_access	entropy_src_tl_errors	8.000s	271.062us	20	20	100.00
V2	tl_d_outstanding_access	entropy_src_csr_hw_reset	4.000s	68.625us	5	5	100.00
		entropy_src_csr_rw	4.000s	65.404us	20	20	100.00
		entropy_src_csr_aliasing	7.000s	146.551us	5	5	100.00
		entropy_src_same_csr_outstanding	5.000s	94.674us	20	20	100.00
V2	tl_d_partial_access	entropy_src_csr_hw_reset	4.000s	68.625us	5	5	100.00
		entropy_src_csr_rw	4.000s	65.404us	20	20	100.00
		entropy_src_csr_aliasing	7.000s	146.551us	5	5	100.00
		entropy_src_same_csr_outstanding	5.000s	94.674us	20	20	100.00
V2		TOTAL			2238	2240	99.91
V2S	tl_intg_err	entropy_src_sec_cm	4.000s	117.832us	5	5	100.00
		entropy_src_tl_intg_err	8.000s	316.944us	20	20	100.00
V2S	sec_cm_config_regwen	entropy_src_rng	11.017m	10.013ms	300	300	100.00
		entropy_src_cfg_regwen	4.000s	35.733us	50	50	100.00
V2S	sec_cm_config_mubi	entropy_src_rng	11.017m	10.013ms	300	300	100.00
V2S	sec_cm_config_redun	entropy_src_rng	11.017m	10.013ms	300	300	100.00
V2S	sec_cm_intersig_mubi	entropy_src_rng	11.017m	10.013ms	300	300	100.00
		entropy_src_fw_ov	2.017m	5.066ms	299	300	99.67
V2S	sec_cm_main_sm_fsm_sparse	entropy_src_functional_errors	5.000s	196.360us	1000	1000	100.00
		entropy_src_sec_cm	4.000s	117.832us	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	entropy_src_functional_errors	5.000s	196.360us	1000	1000	100.00
		entropy_src_sec_cm	4.000s	117.832us	5	5	100.00
V2S	sec_cm_rng_bkgn_chk	entropy_src_rng	11.017m	10.013ms	300	300	100.00
V2S	sec_cm_ctr_redun	entropy_src_functional_errors	5.000s	196.360us	1000	1000	100.00
		entropy_src_sec_cm	4.000s	117.832us	5	5	100.00
V2S	sec_cm_ctr_local_esc	entropy_src_functional_errors	5.000s	196.360us	1000	1000	100.00
V2S	sec_cm_esfinal_rdata_bus_consistency	entropy_src_functional_alerts	5.000s	101.481us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	entropy_src_tl_intg_err	8.000s	316.944us	20	20	100.00
V2S		TOTAL			75	75	100.00
V3	external_health_tests	entropy_src_rng_with_xht_rsps	10.200m	10.014ms	50	50	100.00
V3	stress_all_with_rand_reset	entropy_src_stress_all_with_rand_reset			0	0	--
V3		TOTAL			50	50	100.00
		TOTAL			2468	2470	99.92

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	10	10	8	80.00
V2S	3	3	3	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.42	99.16	97.93	99.78	97.02	99.37	88.29	91.61	95.90

Failure Buckets

UVM_ERROR (entropy_src_scoreboard.sv:1804) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: entropy_src_reg_block.alert_summary_fail_counts has 1 failures:
- Test entropy_src_rng_max_rate has 1 failures.
  - 103.entropy_src_rng_max_rate.1567143426
    Line 512, in log /container/opentitan-public/scratch/os_regression/entropy_src-sim-xcelium/103.entropy_src_rng_max_rate/latest/run.log
```
  UVM_ERROR @ 974820412 ps: (entropy_src_scoreboard.sv:1804) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: entropy_src_reg_block.alert_summary_fail_counts
  UVM_INFO @ 974820412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_entropy_src_*/rtl/entropy_src_core.sv,2990): Assertion AtReset_EsbitFifoPushedIntoPosthtFifo_A has failed has 1 failures:

Test entropy_src_fw_ov has 1 failures.

133.entropy_src_fw_ov.3810368287
Line 743, in log /container/opentitan-public/scratch/os_regression/entropy_src-sim-xcelium/133.entropy_src_fw_ov/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_entropy_src_0.1/rtl/entropy_src_core.sv,2990): (time 3806657840 PS) Assertion tb.dut.u_entropy_src_core.AtReset_EsbitFifoPushedIntoPosthtFifo_A has failed
  UVM_ERROR @ 3806657840 ps: (entropy_src_core.sv:2990) [ASSERT FAILED] AtReset_EsbitFifoPushedIntoPosthtFifo_A
  UVM_INFO @ 3806657840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---