ENTROPY_SRC Simulation Results

Thursday April 04 2024 19:02:33 UTC

GitHub Revision: 2723ca659d

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 9870132716819564205271541124341458297216848204999383102382742091236484427981

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 4.000s 86.309us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 3.000s 82.657us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 4.000s 40.591us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 14.000s 2.128ms 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 8.000s 1.052ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 4.000s 33.698us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 4.000s 40.591us 20 20 100.00
entropy_src_csr_aliasing 8.000s 1.052ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 4.000s 86.309us 50 50 100.00
entropy_src_rng 4.883m 10.031ms 300 300 100.00
entropy_src_fw_ov 2.517m 5.094ms 293 300 97.67
V2 firmware_mode entropy_src_fw_ov 2.517m 5.094ms 293 300 97.67
V2 rng_mode entropy_src_rng 4.883m 10.031ms 300 300 100.00
V2 rng_max_rate entropy_src_rng_max_rate 9.117m 10.027ms 388 400 97.00
V2 health_checks entropy_src_rng 4.883m 10.031ms 300 300 100.00
V2 conditioning entropy_src_rng 4.883m 10.031ms 300 300 100.00
V2 interrupts entropy_src_rng 4.883m 10.031ms 300 300 100.00
V2 alerts entropy_src_rng 4.883m 10.031ms 300 300 100.00
entropy_src_functional_alerts 5.000s 116.864us 50 50 100.00
V2 stress_all entropy_src_stress_all 11.000s 392.245us 50 50 100.00
V2 functional_errors entropy_src_functional_errors 10.567m 10.012ms 968 1000 96.80
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 24.000s 345.140us 50 50 100.00
V2 intr_test entropy_src_intr_test 3.000s 14.695us 50 50 100.00
V2 alert_test entropy_src_alert_test 4.000s 172.926us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 8.000s 691.714us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 8.000s 691.714us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 3.000s 82.657us 5 5 100.00
entropy_src_csr_rw 4.000s 40.591us 20 20 100.00
entropy_src_csr_aliasing 8.000s 1.052ms 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 505.691us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 3.000s 82.657us 5 5 100.00
entropy_src_csr_rw 4.000s 40.591us 20 20 100.00
entropy_src_csr_aliasing 8.000s 1.052ms 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 505.691us 20 20 100.00
V2 TOTAL 2239 2290 97.77
V2S tl_intg_err entropy_src_sec_cm 4.000s 388.334us 5 5 100.00
entropy_src_tl_intg_err 7.000s 221.750us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 4.883m 10.031ms 300 300 100.00
entropy_src_cfg_regwen 3.000s 34.122us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 4.883m 10.031ms 300 300 100.00
V2S sec_cm_config_redun entropy_src_rng 4.883m 10.031ms 300 300 100.00
V2S sec_cm_intersig_mubi entropy_src_rng 4.883m 10.031ms 300 300 100.00
entropy_src_fw_ov 2.517m 5.094ms 293 300 97.67
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 10.567m 10.012ms 968 1000 96.80
entropy_src_sec_cm 4.000s 388.334us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 10.567m 10.012ms 968 1000 96.80
entropy_src_sec_cm 4.000s 388.334us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.883m 10.031ms 300 300 100.00
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 10.567m 10.012ms 968 1000 96.80
entropy_src_sec_cm 4.000s 388.334us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 10.567m 10.012ms 968 1000 96.80
entropy_src_sec_cm 4.000s 388.334us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 10.567m 10.012ms 968 1000 96.80
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 5.000s 116.864us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 7.000s 221.750us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.900m 10.023ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
Unmapped tests entropy_src_intr 23.000s 347.569us 44 50 88.00
TOTAL 2513 2570 97.78

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 11 11 8 72.73
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
86.47 98.17 95.37 98.33 95.84 88.10 96.88 90.46 58.12

Failure Buckets

Past Results