50278df8b| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | flash_ctrl_smoke | 3.218m | 97.996us | 50 | 50 | 100.00 |
| V1 | smoke_hw | flash_ctrl_smoke_hw | 25.970s | 16.726us | 5 | 5 | 100.00 |
| V1 | csr_hw_reset | flash_ctrl_csr_hw_reset | 51.280s | 65.273us | 5 | 5 | 100.00 |
| V1 | csr_rw | flash_ctrl_csr_rw | 19.250s | 108.714us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | flash_ctrl_csr_bit_bash | 1.382m | 3.549ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | flash_ctrl_csr_aliasing | 50.020s | 638.669us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | flash_ctrl_csr_mem_rw_with_rand_reset | 17.870s | 88.154us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | flash_ctrl_csr_rw | 19.250s | 108.714us | 20 | 20 | 100.00 |
| flash_ctrl_csr_aliasing | 50.020s | 638.669us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | flash_ctrl_mem_walk | 13.440s | 61.265us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | flash_ctrl_mem_partial_access | 13.350s | 15.498us | 5 | 5 | 100.00 |
| V1 | TOTAL | 120 | 120 | 100.00 | |||
| V2 | sw_op | flash_ctrl_sw_op | 26.340s | 99.559us | 5 | 5 | 100.00 |
| V2 | host_read_direct | flash_ctrl_host_dir_rd | 2.078m | 472.961us | 4 | 5 | 80.00 |
| V2 | rma_hw_if | flash_ctrl_hw_rma | 30.447m | 125.249ms | 3 | 3 | 100.00 |
| flash_ctrl_hw_rma_reset | 19.270m | 420.347ms | 20 | 20 | 100.00 | ||
| flash_ctrl_lcmgr_intg | 14.600s | 15.576us | 20 | 20 | 100.00 | ||
| V2 | host_controller_arb | flash_ctrl_host_ctrl_arb | 42.015m | 544.431ms | 5 | 5 | 100.00 |
| V2 | erase_suspend | flash_ctrl_erase_suspend | 6.815m | 7.848ms | 5 | 5 | 100.00 |
| V2 | program_reset | flash_ctrl_prog_reset | 3.778m | 3.194ms | 30 | 30 | 100.00 |
| V2 | full_memory_access | flash_ctrl_full_mem_access | 59.800m | 195.639ms | 3 | 5 | 60.00 |
| V2 | rd_buff_eviction | flash_ctrl_rd_buff_evict | 2.512m | 3.050ms | 5 | 5 | 100.00 |
| V2 | rd_buff_eviction_w_ecc | flash_ctrl_rw_evict | 35.920s | 451.151us | 40 | 40 | 100.00 |
| flash_ctrl_rw_evict_all_en | 36.270s | 196.706us | 39 | 40 | 97.50 | ||
| flash_ctrl_re_evict | 39.260s | 875.978us | 19 | 20 | 95.00 | ||
| V2 | host_arb | flash_ctrl_phy_arb | 11.388m | 5.392ms | 20 | 20 | 100.00 |
| V2 | host_interleave | flash_ctrl_phy_arb | 11.388m | 5.392ms | 20 | 20 | 100.00 |
| V2 | memory_protection | flash_ctrl_mp_regions | 14.857m | 32.622ms | 18 | 20 | 90.00 |
| V2 | fetch_code | flash_ctrl_fetch_code | 27.300s | 388.705us | 10 | 10 | 100.00 |
| V2 | all_partitions | flash_ctrl_rand_ops | 22.826m | 214.989us | 20 | 20 | 100.00 |
| V2 | error_mp | flash_ctrl_error_mp | 44.196m | 6.788ms | 10 | 10 | 100.00 |
| V2 | error_prog_win | flash_ctrl_error_prog_win | 17.127m | 7.386ms | 10 | 10 | 100.00 |
| V2 | error_prog_type | flash_ctrl_error_prog_type | 41.793m | 2.514ms | 5 | 5 | 100.00 |
| V2 | error_read_seed | flash_ctrl_hw_read_seed_err | 14.350s | 59.487us | 20 | 20 | 100.00 |
| V2 | read_write_overflow | flash_ctrl_oversize_error | 5.904m | 2.372ms | 5 | 5 | 100.00 |
| V2 | flash_ctrl_disable | flash_ctrl_disable | 26.150s | 69.421us | 50 | 50 | 100.00 |
| V2 | flash_ctrl_connect | flash_ctrl_connect | 19.100s | 16.349us | 80 | 80 | 100.00 |
| V2 | stress_all | flash_ctrl_stress_all | 11.827m | 491.427us | 5 | 5 | 100.00 |
| V2 | secret_partition | flash_ctrl_hw_sec_otp | 4.016m | 3.987ms | 50 | 50 | 100.00 |
| flash_ctrl_otp_reset | 2.491m | 159.158us | 80 | 80 | 100.00 | ||
| V2 | isolation_partition | flash_ctrl_hw_rma | 30.447m | 125.249ms | 3 | 3 | 100.00 |
| V2 | interrupts | flash_ctrl_intr_rd | 7.317m | 3.871ms | 40 | 40 | 100.00 |
| flash_ctrl_intr_wr | 2.553m | 56.408ms | 10 | 10 | 100.00 | ||
| flash_ctrl_intr_rd_slow_flash | 11.855m | 95.241ms | 37 | 40 | 92.50 | ||
| flash_ctrl_intr_wr_slow_flash | 10.724m | 106.660ms | 10 | 10 | 100.00 | ||
| V2 | invalid_op | flash_ctrl_invalid_op | 1.666m | 11.638ms | 20 | 20 | 100.00 |
| V2 | mid_op_rst | flash_ctrl_mid_op_rst | 31.620s | 3.502ms | 5 | 5 | 100.00 |
| V2 | double_bit_err | flash_ctrl_read_word_sweep_derr | 23.140s | 33.745us | 5 | 5 | 100.00 |
| flash_ctrl_ro_derr | 6.083m | 1.775ms | 10 | 10 | 100.00 | ||
| flash_ctrl_rw_derr | 30.364m | 27.324ms | 10 | 10 | 100.00 | ||
| flash_ctrl_derr_detect | 1.816m | 154.917us | 5 | 5 | 100.00 | ||
| flash_ctrl_integrity | 31.736m | 13.832ms | 5 | 5 | 100.00 | ||
| V2 | single_bit_err | flash_ctrl_read_word_sweep_serr | 23.540s | 249.781us | 5 | 5 | 100.00 |
| flash_ctrl_ro_serr | 5.192m | 1.709ms | 10 | 10 | 100.00 | ||
| flash_ctrl_rw_serr | 26.544m | 6.930ms | 10 | 10 | 100.00 | ||
| V2 | singlebit_err_counter | flash_ctrl_serr_counter | 1.270m | 1.516ms | 5 | 5 | 100.00 |
| V2 | singlebit_err_address | flash_ctrl_serr_address | 1.274m | 3.190ms | 5 | 5 | 100.00 |
| V2 | scramble | flash_ctrl_wo | 3.090m | 25.060ms | 20 | 20 | 100.00 |
| flash_ctrl_write_word_sweep | 17.160s | 239.085us | 1 | 1 | 100.00 | ||
| flash_ctrl_read_word_sweep | 14.070s | 25.744us | 1 | 1 | 100.00 | ||
| flash_ctrl_ro | 4.981m | 4.693ms | 20 | 20 | 100.00 | ||
| flash_ctrl_rw | 23.072m | 19.143ms | 20 | 20 | 100.00 | ||
| V2 | filesystem_support | flash_ctrl_fs_sup | 37.400s | 1.206ms | 5 | 5 | 100.00 |
| V2 | rma_write_process_error | flash_ctrl_rma_err | 13.451m | 87.405ms | 3 | 3 | 100.00 |
| flash_ctrl_hw_prog_rma_wipe_err | 4.708m | 10.012ms | 19 | 20 | 95.00 | ||
| V2 | alert_test | flash_ctrl_alert_test | 15.390s | 191.672us | 50 | 50 | 100.00 |
| V2 | intr_test | flash_ctrl_intr_test | 15.230s | 44.182us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | flash_ctrl_tl_errors | 18.890s | 95.108us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | flash_ctrl_tl_errors | 18.890s | 95.108us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | flash_ctrl_csr_hw_reset | 51.280s | 65.273us | 5 | 5 | 100.00 |
| flash_ctrl_csr_rw | 19.250s | 108.714us | 20 | 20 | 100.00 | ||
| flash_ctrl_csr_aliasing | 50.020s | 638.669us | 5 | 5 | 100.00 | ||
| flash_ctrl_same_csr_outstanding | 36.830s | 62.870us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | flash_ctrl_csr_hw_reset | 51.280s | 65.273us | 5 | 5 | 100.00 |
| flash_ctrl_csr_rw | 19.250s | 108.714us | 20 | 20 | 100.00 | ||
| flash_ctrl_csr_aliasing | 50.020s | 638.669us | 5 | 5 | 100.00 | ||
| flash_ctrl_same_csr_outstanding | 36.830s | 62.870us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1002 | 1013 | 98.91 | |||
| V2S | shadow_reg_update_error | flash_ctrl_shadow_reg_errors | 1.741m | 258.380us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | flash_ctrl_shadow_reg_errors | 1.741m | 258.380us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | flash_ctrl_shadow_reg_errors | 1.741m | 258.380us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | flash_ctrl_shadow_reg_errors | 1.741m | 258.380us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | flash_ctrl_shadow_reg_errors_with_csr_rw | 1.930m | 1.066ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | flash_ctrl_sec_cm | 1.364h | 1.545ms | 5 | 5 | 100.00 |
| flash_ctrl_tl_intg_err | 14.929m | 745.817us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_reg_bus_integrity | flash_ctrl_tl_intg_err | 14.929m | 745.817us | 20 | 20 | 100.00 |
| V2S | sec_cm_host_bus_integrity | flash_ctrl_tl_intg_err | 14.929m | 745.817us | 20 | 20 | 100.00 |
| V2S | sec_cm_mem_bus_integrity | flash_ctrl_rd_intg | 31.990s | 62.478us | 3 | 3 | 100.00 |
| flash_ctrl_wr_intg | 15.150s | 253.594us | 2 | 3 | 66.67 | ||
| V2S | sec_cm_scramble_key_sideload | flash_ctrl_smoke | 3.218m | 97.996us | 50 | 50 | 100.00 |
| V2S | sec_cm_lc_ctrl_intersig_mubi | flash_ctrl_otp_reset | 2.491m | 159.158us | 80 | 80 | 100.00 |
| flash_ctrl_disable | 26.150s | 69.421us | 50 | 50 | 100.00 | ||
| flash_ctrl_sec_info_access | 1.504m | 19.415ms | 50 | 50 | 100.00 | ||
| flash_ctrl_connect | 19.100s | 16.349us | 80 | 80 | 100.00 | ||
| V2S | sec_cm_ctrl_config_regwen | flash_ctrl_config_regwen | 13.870s | 74.164us | 5 | 5 | 100.00 |
| V2S | sec_cm_data_regions_config_regwen | flash_ctrl_csr_rw | 19.250s | 108.714us | 20 | 20 | 100.00 |
| V2S | sec_cm_data_regions_config_shadow | flash_ctrl_shadow_reg_errors | 1.741m | 258.380us | 20 | 20 | 100.00 |
| V2S | sec_cm_info_regions_config_regwen | flash_ctrl_csr_rw | 19.250s | 108.714us | 20 | 20 | 100.00 |
| V2S | sec_cm_info_regions_config_shadow | flash_ctrl_shadow_reg_errors | 1.741m | 258.380us | 20 | 20 | 100.00 |
| V2S | sec_cm_bank_config_regwen | flash_ctrl_csr_rw | 19.250s | 108.714us | 20 | 20 | 100.00 |
| V2S | sec_cm_bank_config_shadow | flash_ctrl_shadow_reg_errors | 1.741m | 258.380us | 20 | 20 | 100.00 |
| V2S | sec_cm_mem_ctrl_global_esc | flash_ctrl_disable | 26.150s | 69.421us | 50 | 50 | 100.00 |
| V2S | sec_cm_mem_ctrl_local_esc | flash_ctrl_rd_intg | 31.990s | 62.478us | 3 | 3 | 100.00 |
| flash_ctrl_access_after_disable | 13.600s | 13.956us | 3 | 3 | 100.00 | ||
| V2S | sec_cm_mem_disable_config_mubi | flash_ctrl_disable | 26.150s | 69.421us | 50 | 50 | 100.00 |
| V2S | sec_cm_exec_config_redun | flash_ctrl_fetch_code | 27.300s | 388.705us | 10 | 10 | 100.00 |
| V2S | sec_cm_mem_scramble | flash_ctrl_rw | 23.072m | 19.143ms | 20 | 20 | 100.00 |
| V2S | sec_cm_mem_integrity | flash_ctrl_rw_serr | 26.544m | 6.930ms | 10 | 10 | 100.00 |
| flash_ctrl_rw_derr | 30.364m | 27.324ms | 10 | 10 | 100.00 | ||
| flash_ctrl_integrity | 31.736m | 13.832ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_rma_entry_mem_sec_wipe | flash_ctrl_hw_rma | 30.447m | 125.249ms | 3 | 3 | 100.00 |
| V2S | sec_cm_ctrl_fsm_sparse | flash_ctrl_sec_cm | 1.364h | 1.545ms | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_fsm_sparse | flash_ctrl_sec_cm | 1.364h | 1.545ms | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_prog_fsm_sparse | flash_ctrl_sec_cm | 1.364h | 1.545ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | flash_ctrl_sec_cm | 1.364h | 1.545ms | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_arbiter_ctrl_redun | flash_ctrl_phy_arb_redun | 14.310s | 54.641us | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_host_grant_ctrl_consistency | flash_ctrl_phy_host_grant_err | 13.810s | 17.409us | 3 | 5 | 60.00 |
| V2S | sec_cm_phy_ack_ctrl_consistency | flash_ctrl_phy_ack_consistency | 14.160s | 25.812us | 4 | 5 | 80.00 |
| V2S | sec_cm_fifo_ctr_redun | flash_ctrl_sec_cm | 1.364h | 1.545ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | flash_ctrl_sec_cm | 1.364h | 1.545ms | 5 | 5 | 100.00 |
| V2S | sec_cm_prog_tl_lc_gate_fsm_sparse | flash_ctrl_sec_cm | 1.364h | 1.545ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 140 | 144 | 97.22 | |||
| V3 | asymmetric_read_path | flash_ctrl_rd_ooo | 43.140s | 52.366us | 1 | 1 | 100.00 |
| V3 | stress_all_with_rand_reset | flash_ctrl_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 1 | 1 | 100.00 | |||
| TOTAL | 1263 | 1278 | 98.83 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 9 | 100.00 |
| V2 | 55 | 55 | 48 | 87.27 |
| V2S | 12 | 12 | 9 | 75.00 |
| V3 | 2 | 1 | 1 | 50.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.57 | 95.49 | 94.28 | 98.95 | 92.52 | 97.32 | 98.62 | 98.78 |
UVM_FATAL (flash_phy_prim_monitor.sv:44) [monitor] timeout waiting for mon_start has 3 failures:
15.flash_ctrl_intr_rd_slow_flash.1579652623
Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_intr_rd_slow_flash/latest/run.log
UVM_FATAL @ 200000.0 ns: (flash_phy_prim_monitor.sv:44) [uvm_test_top.env.m_fpp_agent.monitor] timeout waiting for mon_start
UVM_INFO @ 200000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.flash_ctrl_intr_rd_slow_flash.4235099404
Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_intr_rd_slow_flash/latest/run.log
UVM_FATAL @ 200000.0 ns: (flash_phy_prim_monitor.sv:44) [uvm_test_top.env.m_fpp_agent.monitor] timeout waiting for mon_start
UVM_INFO @ 200000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
2.flash_ctrl_full_mem_access.3060356437
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_full_mem_access/latest/run.log
Job ID: smart:71a415b5-ccc9-435e-816c-317b6660085e
4.flash_ctrl_full_mem_access.2632692176
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_full_mem_access/latest/run.log
Job ID: smart:7a248b38-93f3-4bd5-968f-dd2333b302d7
UVM_ERROR (flash_ctrl_scoreboard.sv:190) [scoreboard] Check failed exp_data[*] == trans.d_data (* [*] vs * [*]) has 1 failures:
0.flash_ctrl_host_dir_rd.1358256768
Line 267, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_host_dir_rd/latest/run.log
UVM_ERROR @ 34726.5 ns: (flash_ctrl_scoreboard.sv:190) [uvm_test_top.env.scoreboard] Check failed exp_data[0] == trans.d_data (634992721 [0x25d93851] vs 2703233029 [0xa1201005])
UVM_INFO @ 34726.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:221) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_std_err triggered unexpectedly has 1 failures:
0.flash_ctrl_phy_ack_consistency.691565759
Line 262, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_phy_ack_consistency/latest/run.log
UVM_ERROR @ 6102.3 ns: (cip_base_scoreboard.sv:221) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_std_err triggered unexpectedly
UVM_INFO @ 6102.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:479) [lm_wdata_comp_bank1] Check failed rcv.mem_addr == exp.req.addr (* [*] vs * [*]) has 1 failures:
0.flash_ctrl_hw_prog_rma_wipe_err.2444016023
Line 269, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_hw_prog_rma_wipe_err/latest/run.log
UVM_ERROR @ 10005227.1 ns: (flash_ctrl_otf_scoreboard.sv:479) [lm_wdata_comp_bank1] Check failed rcv.mem_addr == exp.req.addr (0 [0x0] vs 28877 [0x70cd])
UVM_INFO @ 10005227.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:365) [wdata_page0_comp_bank0] *: obs:exp *b_*_c766321f_d2b9e3c8:7d_*_7d9434fd_66a09a* mismatch!! has 1 failures:
1.flash_ctrl_wr_intg.1460001975
Line 273, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_wr_intg/latest/run.log
UVM_ERROR @ 97583.9 ns: (flash_ctrl_otf_scoreboard.sv:365) [wdata_page0_comp_bank0] 0: obs:exp 5b_7_c766321f_d2b9e3c8:7d_9_7d9434fd_66a09a79 mismatch!!
UVM_INFO @ 97583.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$isunknown(mem_tl_o))' has 1 failures:
2.flash_ctrl_phy_host_grant_err.2385028953
Line 262, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_phy_host_grant_err/latest/run.log
Offending '(!$isunknown(mem_tl_o))'
UVM_ERROR @ 5523.0 ns: (flash_ctrl.sv:1399) [ASSERT FAILED] MemRspPayLoad_A
UVM_INFO @ 5523.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$isunknown(mem_tl_o.d_valid))' has 1 failures:
4.flash_ctrl_phy_host_grant_err.3884804134
Line 262, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_phy_host_grant_err/latest/run.log
Offending '(!$isunknown(mem_tl_o.d_valid))'
UVM_ERROR @ 18227.2 ns: (flash_ctrl.sv:1397) [ASSERT FAILED] MemTlDValidKnownO_A
UVM_INFO @ 18227.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:281) scoreboard [scoreboard] alert recov_err did not trigger max_delay:* has 1 failures:
5.flash_ctrl_mp_regions.1085201549
Line 1673, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_mp_regions/latest/run.log
UVM_ERROR @ 271263.3 ns: (cip_base_scoreboard.sv:281) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_err did not trigger max_delay:2000
UVM_INFO @ 271263.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:373) [rdata_comp_bank0] *: obs:exp ee734d66_50cbd1d8:ea100e8f_5cc3ac0d mismatch!! has 1 failures:
12.flash_ctrl_re_evict.1215348529
Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_re_evict/latest/run.log
UVM_ERROR @ 73819.0 ns: (flash_ctrl_otf_scoreboard.sv:373) [rdata_comp_bank0] 4: obs:exp ee734d66_50cbd1d8:ea100e8f_5cc3ac0d mismatch!!
UVM_INFO @ 73819.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (flash_ctrl_mp_regions_vseq.sv:196) [flash_ctrl_mp_regions_vseq] wait timeout for alert_count == exp_alertcnt after do_mp_reg() alert_cnt:* exp_alert_cnt:* has 1 failures:
17.flash_ctrl_mp_regions.998342264
Line 395, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_mp_regions/latest/run.log
UVM_FATAL @ 253476.7 ns: (flash_ctrl_mp_regions_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.flash_ctrl_mp_regions_vseq] wait timeout for alert_count == exp_alertcnt after do_mp_reg() alert_cnt:9 exp_alert_cnt:10
UVM_INFO @ 253476.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 1 failures:
22.flash_ctrl_rw_evict_all_en.2936065288
Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/22.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_ERROR @ 11887.0 ns: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
UVM_INFO @ 11887.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---