FLASH_CTRL Simulation Results

Tuesday May 30 2023 07:03:17 UTC

GitHub Revision: f8b3c19a2

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1284268927

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke flash_ctrl_smoke 4.515m 760.367us 50 50 100.00
V1 smoke_hw flash_ctrl_smoke_hw 26.140s 15.216us 5 5 100.00
V1 csr_hw_reset flash_ctrl_csr_hw_reset 45.840s 284.824us 5 5 100.00
V1 csr_rw flash_ctrl_csr_rw 18.990s 67.556us 20 20 100.00
V1 csr_bit_bash flash_ctrl_csr_bit_bash 1.164m 2.199ms 5 5 100.00
V1 csr_aliasing flash_ctrl_csr_aliasing 51.440s 449.531us 5 5 100.00
V1 csr_mem_rw_with_rand_reset flash_ctrl_csr_mem_rw_with_rand_reset 19.080s 79.403us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr flash_ctrl_csr_rw 18.990s 67.556us 20 20 100.00
flash_ctrl_csr_aliasing 51.440s 449.531us 5 5 100.00
V1 mem_walk flash_ctrl_mem_walk 13.620s 14.761us 5 5 100.00
V1 mem_partial_access flash_ctrl_mem_partial_access 13.810s 18.017us 5 5 100.00
V1 TOTAL 120 120 100.00
V2 sw_op flash_ctrl_sw_op 26.620s 43.638us 5 5 100.00
V2 host_read_direct flash_ctrl_host_dir_rd 2.047m 264.060us 5 5 100.00
V2 rma_hw_if flash_ctrl_hw_rma 28.974m 93.854ms 3 3 100.00
flash_ctrl_hw_rma_reset 20.660m 480.337ms 20 20 100.00
flash_ctrl_lcmgr_intg 14.480s 27.319us 20 20 100.00
V2 host_controller_arb flash_ctrl_host_ctrl_arb 40.955m 491.056ms 5 5 100.00
V2 erase_suspend flash_ctrl_erase_suspend 8.560m 13.414ms 5 5 100.00
V2 program_reset flash_ctrl_prog_reset 5.248m 4.040ms 30 30 100.00
V2 full_memory_access flash_ctrl_full_mem_access 47.919m 187.457ms 4 5 80.00
V2 rd_buff_eviction flash_ctrl_rd_buff_evict 2.535m 707.112us 5 5 100.00
V2 rd_buff_eviction_w_ecc flash_ctrl_rw_evict 36.810s 138.314us 39 40 97.50
flash_ctrl_rw_evict_all_en 37.230s 231.443us 40 40 100.00
flash_ctrl_re_evict 40.530s 2.247ms 20 20 100.00
V2 host_arb flash_ctrl_phy_arb 9.606m 2.918ms 20 20 100.00
V2 host_interleave flash_ctrl_phy_arb 9.606m 2.918ms 20 20 100.00
V2 memory_protection flash_ctrl_mp_regions 20.167m 84.311ms 20 20 100.00
V2 fetch_code flash_ctrl_fetch_code 27.720s 2.031ms 10 10 100.00
V2 all_partitions flash_ctrl_rand_ops 18.324m 545.055us 19 20 95.00
V2 error_mp flash_ctrl_error_mp 41.406m 17.250ms 10 10 100.00
V2 error_prog_win flash_ctrl_error_prog_win 17.258m 419.150us 10 10 100.00
V2 error_prog_type flash_ctrl_error_prog_type 45.422m 1.014ms 5 5 100.00
V2 error_read_seed flash_ctrl_hw_read_seed_err 13.930s 14.880us 20 20 100.00
V2 read_write_overflow flash_ctrl_oversize_error 7.518m 14.412ms 5 5 100.00
V2 flash_ctrl_disable flash_ctrl_disable 23.900s 26.246us 50 50 100.00
V2 flash_ctrl_connect flash_ctrl_connect 16.650s 35.194us 80 80 100.00
V2 stress_all flash_ctrl_stress_all 29.636m 1.078ms 5 5 100.00
V2 secret_partition flash_ctrl_hw_sec_otp 4.271m 30.335ms 50 50 100.00
flash_ctrl_otp_reset 2.722m 80.915us 80 80 100.00
V2 isolation_partition flash_ctrl_hw_rma 28.974m 93.854ms 3 3 100.00
V2 interrupts flash_ctrl_intr_rd 6.862m 2.055ms 40 40 100.00
flash_ctrl_intr_wr 2.071m 18.286ms 10 10 100.00
flash_ctrl_intr_rd_slow_flash 10.607m 91.733ms 36 40 90.00
flash_ctrl_intr_wr_slow_flash 7.497m 43.738ms 10 10 100.00
V2 invalid_op flash_ctrl_invalid_op 1.591m 3.776ms 16 20 80.00
V2 mid_op_rst flash_ctrl_mid_op_rst 33.930s 1.452ms 5 5 100.00
V2 double_bit_err flash_ctrl_read_word_sweep_derr 23.040s 56.499us 5 5 100.00
flash_ctrl_ro_derr 6.530m 1.763ms 10 10 100.00
flash_ctrl_rw_derr 31.133m 6.880ms 10 10 100.00
flash_ctrl_derr_detect 1.835m 400.528us 5 5 100.00
flash_ctrl_integrity 30.977m 14.311ms 5 5 100.00
V2 single_bit_err flash_ctrl_read_word_sweep_serr 22.680s 24.744us 5 5 100.00
flash_ctrl_ro_serr 6.014m 16.392ms 10 10 100.00
flash_ctrl_rw_serr 29.178m 12.849ms 10 10 100.00
V2 singlebit_err_counter flash_ctrl_serr_counter 1.729m 14.433ms 5 5 100.00
V2 singlebit_err_address flash_ctrl_serr_address 1.524m 4.744ms 5 5 100.00
V2 scramble flash_ctrl_wo 3.467m 3.930ms 20 20 100.00
flash_ctrl_write_word_sweep 17.110s 119.298us 1 1 100.00
flash_ctrl_read_word_sweep 13.320s 125.987us 1 1 100.00
flash_ctrl_ro 4.929m 2.862ms 20 20 100.00
flash_ctrl_rw 23.863m 78.896ms 20 20 100.00
V2 filesystem_support flash_ctrl_fs_sup 38.820s 1.934ms 5 5 100.00
V2 rma_write_process_error flash_ctrl_rma_err 14.757m 103.087ms 3 3 100.00
flash_ctrl_hw_prog_rma_wipe_err 4.519m 10.013ms 20 20 100.00
V2 alert_test flash_ctrl_alert_test 14.460s 138.971us 50 50 100.00
V2 intr_test flash_ctrl_intr_test 14.750s 17.482us 50 50 100.00
V2 tl_d_oob_addr_access flash_ctrl_tl_errors 19.620s 104.976us 20 20 100.00
V2 tl_d_illegal_access flash_ctrl_tl_errors 19.620s 104.976us 20 20 100.00
V2 tl_d_outstanding_access flash_ctrl_csr_hw_reset 45.840s 284.824us 5 5 100.00
flash_ctrl_csr_rw 18.990s 67.556us 20 20 100.00
flash_ctrl_csr_aliasing 51.440s 449.531us 5 5 100.00
flash_ctrl_same_csr_outstanding 35.570s 1.617ms 20 20 100.00
V2 tl_d_partial_access flash_ctrl_csr_hw_reset 45.840s 284.824us 5 5 100.00
flash_ctrl_csr_rw 18.990s 67.556us 20 20 100.00
flash_ctrl_csr_aliasing 51.440s 449.531us 5 5 100.00
flash_ctrl_same_csr_outstanding 35.570s 1.617ms 20 20 100.00
V2 TOTAL 1002 1013 98.91
V2S shadow_reg_update_error flash_ctrl_shadow_reg_errors 1.740m 115.223us 20 20 100.00
V2S shadow_reg_read_clear_staged_value flash_ctrl_shadow_reg_errors 1.740m 115.223us 20 20 100.00
V2S shadow_reg_storage_error flash_ctrl_shadow_reg_errors 1.740m 115.223us 20 20 100.00
V2S shadowed_reset_glitch flash_ctrl_shadow_reg_errors 1.740m 115.223us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw flash_ctrl_shadow_reg_errors_with_csr_rw 2.575m 221.827us 20 20 100.00
V2S tl_intg_err flash_ctrl_sec_cm 1.379h 1.286ms 5 5 100.00
flash_ctrl_tl_intg_err 17.333m 4.284ms 20 20 100.00
V2S sec_cm_reg_bus_integrity flash_ctrl_tl_intg_err 17.333m 4.284ms 20 20 100.00
V2S sec_cm_host_bus_integrity flash_ctrl_tl_intg_err 17.333m 4.284ms 20 20 100.00
V2S sec_cm_mem_bus_integrity flash_ctrl_rd_intg 32.570s 63.831us 3 3 100.00
flash_ctrl_wr_intg 14.980s 97.394us 3 3 100.00
V2S sec_cm_scramble_key_sideload flash_ctrl_smoke 4.515m 760.367us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi flash_ctrl_otp_reset 2.722m 80.915us 80 80 100.00
flash_ctrl_disable 23.900s 26.246us 50 50 100.00
flash_ctrl_sec_info_access 1.374m 2.545ms 50 50 100.00
flash_ctrl_connect 16.650s 35.194us 80 80 100.00
V2S sec_cm_ctrl_config_regwen flash_ctrl_config_regwen 13.980s 71.042us 5 5 100.00
V2S sec_cm_data_regions_config_regwen flash_ctrl_csr_rw 18.990s 67.556us 20 20 100.00
V2S sec_cm_data_regions_config_shadow flash_ctrl_shadow_reg_errors 1.740m 115.223us 20 20 100.00
V2S sec_cm_info_regions_config_regwen flash_ctrl_csr_rw 18.990s 67.556us 20 20 100.00
V2S sec_cm_info_regions_config_shadow flash_ctrl_shadow_reg_errors 1.740m 115.223us 20 20 100.00
V2S sec_cm_bank_config_regwen flash_ctrl_csr_rw 18.990s 67.556us 20 20 100.00
V2S sec_cm_bank_config_shadow flash_ctrl_shadow_reg_errors 1.740m 115.223us 20 20 100.00
V2S sec_cm_mem_ctrl_global_esc flash_ctrl_disable 23.900s 26.246us 50 50 100.00
V2S sec_cm_mem_ctrl_local_esc flash_ctrl_rd_intg 32.570s 63.831us 3 3 100.00
flash_ctrl_access_after_disable 13.790s 13.623us 3 3 100.00
V2S sec_cm_mem_disable_config_mubi flash_ctrl_disable 23.900s 26.246us 50 50 100.00
V2S sec_cm_exec_config_redun flash_ctrl_fetch_code 27.720s 2.031ms 10 10 100.00
V2S sec_cm_mem_scramble flash_ctrl_rw 23.863m 78.896ms 20 20 100.00
V2S sec_cm_mem_integrity flash_ctrl_rw_serr 29.178m 12.849ms 10 10 100.00
flash_ctrl_rw_derr 31.133m 6.880ms 10 10 100.00
flash_ctrl_integrity 30.977m 14.311ms 5 5 100.00
V2S sec_cm_rma_entry_mem_sec_wipe flash_ctrl_hw_rma 28.974m 93.854ms 3 3 100.00
V2S sec_cm_ctrl_fsm_sparse flash_ctrl_sec_cm 1.379h 1.286ms 5 5 100.00
V2S sec_cm_phy_fsm_sparse flash_ctrl_sec_cm 1.379h 1.286ms 5 5 100.00
V2S sec_cm_phy_prog_fsm_sparse flash_ctrl_sec_cm 1.379h 1.286ms 5 5 100.00
V2S sec_cm_ctr_redun flash_ctrl_sec_cm 1.379h 1.286ms 5 5 100.00
V2S sec_cm_phy_arbiter_ctrl_redun flash_ctrl_phy_arb_redun 14.650s 20.573us 5 5 100.00
V2S sec_cm_phy_host_grant_ctrl_consistency flash_ctrl_phy_host_grant_err 14.230s 24.891us 2 5 40.00
V2S sec_cm_phy_ack_ctrl_consistency flash_ctrl_phy_ack_consistency 15.110s 49.753us 3 5 60.00
V2S sec_cm_fifo_ctr_redun flash_ctrl_sec_cm 1.379h 1.286ms 5 5 100.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse flash_ctrl_sec_cm 1.379h 1.286ms 5 5 100.00
V2S sec_cm_prog_tl_lc_gate_fsm_sparse flash_ctrl_sec_cm 1.379h 1.286ms 5 5 100.00
V2S TOTAL 139 144 96.53
V3 asymmetric_read_path flash_ctrl_rd_ooo 47.730s 120.837us 1 1 100.00
V3 stress_all_with_rand_reset flash_ctrl_stress_all_with_rand_reset 0 0 --
V3 TOTAL 1 1 100.00
TOTAL 1262 1278 98.75

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 55 55 50 90.91
V2S 12 12 10 83.33
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
96.50 95.50 94.35 98.95 92.52 97.36 98.30 98.55

Failure Buckets

Past Results