FLASH_CTRL Simulation Results

Thursday May 09 2024 19:02:32 UTC

GitHub Revision: `9656691e03`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 30170103562476460183108208532025718695603957360441815475011549460912256789439

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	2.759m	85.075us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.150s	15.553us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	47.220s	200.688us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	18.080s	67.812us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.335m	4.807ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.108m	1.610ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	19.830s	388.535us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	18.080s	67.812us	20	20	100.00
		flash_ctrl_csr_aliasing	1.108m	1.610ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.810s	16.423us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	14.040s	59.979us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	27.100s	22.076us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.009m	291.457us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	35.672m	334.254ms	3	3	100.00
		flash_ctrl_hw_rma_reset	17.806m	420.313ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.740s	48.428us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	41.570m	250.734ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	7.029m	4.252ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	20.390s	107.421us	5	30	16.67
V2	full_memory_access	flash_ctrl_full_mem_access	1.158h	50.869ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.539m	790.010us	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	32.120s	42.170us	3	40	7.50
		flash_ctrl_rw_evict_all_en	31.760s	42.807us	11	40	27.50
		flash_ctrl_re_evict	39.640s	120.021us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	9.556m	4.064ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	9.556m	4.064ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	15.210m	56.174ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	25.160s	268.254us	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	24.172m	628.221us	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	45.126m	7.891ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	18.870m	3.203ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	53.606m	817.884us	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	14.060s	16.128us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	4.094m	10.019ms	0	5	0.00
V2	flash_ctrl_disable	flash_ctrl_disable	23.020s	35.521us	30	50	60.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.600s	15.658us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	28.244m	2.072ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	3.873m	2.873ms	50	50	100.00
		flash_ctrl_otp_reset	2.264m	43.178us	79	80	98.75
V2	isolation_partition	flash_ctrl_hw_rma	35.672m	334.254ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	3.810m	1.324ms	40	40	100.00
		flash_ctrl_intr_wr	16.280s	164.832us	0	10	0.00
		flash_ctrl_intr_rd_slow_flash	4.830m	140.467ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	35.300s	3.044ms	0	10	0.00
V2	invalid_op	flash_ctrl_invalid_op	1.461m	2.034ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.270m	4.308ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.130s	61.301us	5	5	100.00
		flash_ctrl_ro_derr	2.813m	9.064ms	10	10	100.00
		flash_ctrl_rw_derr	7.267m	8.501ms	0	10	0.00
		flash_ctrl_derr_detect	1.049m	143.753us	0	5	0.00
		flash_ctrl_integrity	5.530m	14.153ms	0	5	0.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.790s	24.109us	5	5	100.00
		flash_ctrl_ro_serr	2.699m	1.364ms	10	10	100.00
		flash_ctrl_rw_serr	2.992m	2.746ms	0	10	0.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.359m	1.442ms	0	5	0.00
V2	singlebit_err_address	flash_ctrl_serr_address	55.770s	450.626us	0	5	0.00
V2	scramble	flash_ctrl_wo	4.612m	35.121ms	20	20	100.00
		flash_ctrl_write_word_sweep	13.370s	90.410us	0	1	0.00
		flash_ctrl_read_word_sweep	14.740s	104.614us	1	1	100.00
		flash_ctrl_ro	2.512m	2.734ms	18	20	90.00
		flash_ctrl_rw	11.066m	20.443ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	36.730s	312.117us	2	5	40.00
V2	rma_write_process_error	flash_ctrl_rma_err	17.059m	57.452ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	2.642m	10.020ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	15.480s	519.035us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.300s	18.040us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.560s	244.393us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.560s	244.393us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	47.220s	200.688us	5	5	100.00
		flash_ctrl_csr_rw	18.080s	67.812us	20	20	100.00
		flash_ctrl_csr_aliasing	1.108m	1.610ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.280s	193.311us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	47.220s	200.688us	5	5	100.00
		flash_ctrl_csr_rw	18.080s	67.812us	20	20	100.00
		flash_ctrl_csr_aliasing	1.108m	1.610ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.280s	193.311us	20	20	100.00
V2		TOTAL			830	1013	81.93
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.170s	45.338us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.170s	45.338us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.170s	45.338us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.170s	45.338us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.610s	32.001us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	29.970s	9.538us	0	5	0.00
		flash_ctrl_tl_intg_err	15.307m	1.420ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.307m	1.420ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.307m	1.420ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.560s	64.956us	3	3	100.00
		flash_ctrl_wr_intg	15.000s	381.445us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	2.759m	85.075us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.264m	43.178us	79	80	98.75
		flash_ctrl_disable	23.020s	35.521us	30	50	60.00
		flash_ctrl_sec_info_access	1.341m	12.848ms	50	50	100.00
		flash_ctrl_connect	16.600s	15.658us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.180s	77.099us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	18.080s	67.812us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.170s	45.338us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	18.080s	67.812us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.170s	45.338us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	18.080s	67.812us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.170s	45.338us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	23.020s	35.521us	30	50	60.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.560s	64.956us	3	3	100.00
		flash_ctrl_access_after_disable	13.530s	7.305us	1	3	33.33
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	23.020s	35.521us	30	50	60.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	25.160s	268.254us	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.066m	20.443ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	2.992m	2.746ms	0	10	0.00
		flash_ctrl_rw_derr	7.267m	8.501ms	0	10	0.00
		flash_ctrl_integrity	5.530m	14.153ms	0	5	0.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	35.672m	334.254ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	29.970s	9.538us	0	5	0.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	29.970s	9.538us	0	5	0.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	29.970s	9.538us	0	5	0.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	29.970s	9.538us	0	5	0.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	26.600s	826.349us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	15.160s	23.840us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	15.330s	103.478us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	29.970s	9.538us	0	5	0.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	29.970s	9.538us	0	5	0.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	29.970s	9.538us	0	5	0.00
V2S		TOTAL			137	144	95.14
V3	asymmetric_read_path	flash_ctrl_rd_ooo	46.560s	526.469us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1088	1278	85.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	38	69.09
V2S	12	12	10	83.33
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.99	95.74	93.52	94.81	90.48	97.86	94.71	97.78

Failure Buckets

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_rw_evict_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 46 failures:

Test flash_ctrl_rw_evict_all_en has 24 failures.

0.flash_ctrl_rw_evict_all_en.57476602350308303170652826115250034008846486918274850642841841191783802448077
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_ERROR @ 19699.0 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 19699.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.flash_ctrl_rw_evict_all_en.107078021102075975915884900706341460065927839997986601838142829514571823539481
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_ERROR @ 58228.3 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 58228.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 22 more failures.

Test flash_ctrl_rw_evict has 22 failures.

2.flash_ctrl_rw_evict.97354164396676718820545256555182388048922403058928111551278201603840732961689
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 19719.7 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 19719.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.flash_ctrl_rw_evict.48769907966730896438967028431027254478037403602313646070085901597556111797861
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 23821.6 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 23821.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 20 more failures.

UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_rw_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 25 failures:

Test flash_ctrl_rw_serr has 10 failures.

0.flash_ctrl_rw_serr.71854430454232002041498723954685928784285766804608177929915188828102749980385
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_serr/latest/run.log

  UVM_FATAL @ 207941.8 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000015b0
  UVM_INFO @ 207941.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_rw_serr.44679774629346359423518561186038915206489760368498502320528162192172945192760
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_serr/latest/run.log

  UVM_FATAL @ 278920.2 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000000f8
  UVM_INFO @ 278920.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test flash_ctrl_rw_derr has 10 failures.

0.flash_ctrl_rw_derr.85632338281095596181714214306037259765234769552786851830888660758482840148577
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_derr/latest/run.log

  UVM_FATAL @ 464130.9 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000048e8
  UVM_INFO @ 464130.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_rw_derr.35603083613827596745178601324273052912685046424556698119016723489596890351287
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_derr/latest/run.log

  UVM_FATAL @ 739506.7 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00002840
  UVM_INFO @ 739506.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test flash_ctrl_integrity has 5 failures.

0.flash_ctrl_integrity.18263724808658001245698686161928020748050672445438599466601871067471969823969
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_integrity/latest/run.log

  UVM_FATAL @ 319692.2 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00003f38
  UVM_INFO @ 319692.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_integrity.32764186547757252606512638167624059074161198290728138805771260915405497147821
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_integrity/latest/run.log

  UVM_FATAL @ 1270784.1 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00003b38
  UVM_INFO @ 1270784.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:405) [flash_ctrl_rw_evict_vseq] Check failed (wd % * == *) prog_flash gets unexpected odd bus word count has 17 failures:

Test flash_ctrl_rw_evict has 13 failures.

0.flash_ctrl_rw_evict.48902440274699478935616590464682279917509362430737766738092963413378528390238
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 21295.0 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 21295.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.flash_ctrl_rw_evict.25835337213942266821656746062122755634764642932127475497747862922382368236692
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 43715.7 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 43715.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 11 more failures.

Test flash_ctrl_rw_evict_all_en has 4 failures.

2.flash_ctrl_rw_evict_all_en.40739413884719915236700581820393279932853874599734397547270844103768605396954
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_ERROR @ 14699.0 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 14699.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.flash_ctrl_rw_evict_all_en.96345393560951333075767379142484199507535675665341041907680870645096913399377
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_ERROR @ 48012.5 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 48012.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_intr_wr_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 15 failures:

Test flash_ctrl_intr_wr_slow_flash has 7 failures.

0.flash_ctrl_intr_wr_slow_flash.50734980269191920430078860345223401891628986217739621340300401853149160968550
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_intr_wr_slow_flash/latest/run.log

  UVM_ERROR @ 20399.8 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_intr_wr_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 20399.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.flash_ctrl_intr_wr_slow_flash.60162509504527691895707239366443292446229436005959032987616210482605607888174
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_intr_wr_slow_flash/latest/run.log

  UVM_ERROR @ 84053.9 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_intr_wr_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 84053.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test flash_ctrl_intr_wr has 8 failures.

1.flash_ctrl_intr_wr.38677954739375283327099312012206354291445738415330979476170846906421593028118
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_intr_wr/latest/run.log

  UVM_ERROR @ 24326.8 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_intr_wr_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 24326.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.flash_ctrl_intr_wr.15496114129845080231566831283057010150343406242146762617442743484949381882609
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_intr_wr/latest/run.log

  UVM_ERROR @ 30539.1 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_intr_wr_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 30539.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_prog_reset_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 13 failures:

Test flash_ctrl_prog_reset has 13 failures.

0.flash_ctrl_prog_reset.29569693160579499759277197903238485681015724964797655189177893049261484414687
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_prog_reset/latest/run.log

  UVM_ERROR @ 17552.3 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_prog_reset_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 17552.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.flash_ctrl_prog_reset.52510357522476616612016709267333120313960359134541968160125264143218585110869
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_prog_reset/latest/run.log

  UVM_ERROR @ 8919.5 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_prog_reset_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 8919.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 11 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_disable_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 12 failures:

Test flash_ctrl_disable has 12 failures.

1.flash_ctrl_disable.31766585716524382863391638403744234023722614616625351815455319695997398782367
Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_disable/latest/run.log

  UVM_ERROR @ 9492.3 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_disable_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 9492.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.flash_ctrl_disable.102779096342108704438202616894179347385636226476862411015861324163408004789084
Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_disable/latest/run.log

  UVM_ERROR @ 9575.9 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_disable_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 9575.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 10 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:405) [flash_ctrl_prog_reset_vseq] Check failed (wd % * == *) prog_flash gets unexpected odd bus word count has 8 failures:
- Test flash_ctrl_prog_reset has 8 failures.
  - 4.flash_ctrl_prog_reset.74006617704787220344863004488379655545905731428605885779258550428717987636114
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_prog_reset/latest/run.log
```
  UVM_ERROR @ 9027.3 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_prog_reset_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 9027.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.flash_ctrl_prog_reset.102799934981245748258266145485840383535891103234534996384216751057923276098942
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_prog_reset/latest/run.log
```
  UVM_ERROR @ 32337.6 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_prog_reset_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 32337.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_ERROR (flash_ctrl_otf_base_vseq.sv:405) [flash_ctrl_disable_vseq] Check failed (wd % * == *) prog_flash gets unexpected odd bus word count has 6 failures:
- Test flash_ctrl_disable has 6 failures.
  - 6.flash_ctrl_disable.60165032759567066266896348586507470058789647008063727360416783674643150930182
    Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_disable/latest/run.log
```
  UVM_ERROR @ 22358.9 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_disable_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 22358.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.flash_ctrl_disable.49589024049397289000980289201595201711427350344316074292442779098689192982918
    Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_disable/latest/run.log
```
  UVM_ERROR @ 35859.2 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_disable_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 35859.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_serr_counter_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 5 failures:
- Test flash_ctrl_serr_counter has 5 failures.
  - 0.flash_ctrl_serr_counter.62405029729782430898596074632863427283905305682818507967485064744129182954136
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_serr_counter/latest/run.log
```
  UVM_FATAL @ 497589.1 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_serr_counter_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00004100
  UVM_INFO @ 497589.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.flash_ctrl_serr_counter.53647809558903497953747521936745575911345488640965895431276895606845789262591
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_serr_counter/latest/run.log
```
  UVM_FATAL @ 1679335.4 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_serr_counter_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000030c8
  UVM_INFO @ 1679335.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_serr_address_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 5 failures:
- Test flash_ctrl_serr_address has 5 failures.
  - 0.flash_ctrl_serr_address.31643393481573962794494631443255829342899497408588174512349275054132539264113
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_serr_address/latest/run.log
```
  UVM_FATAL @ 229273.0 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_serr_address_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00002958
  UVM_INFO @ 229273.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.flash_ctrl_serr_address.46074612526054576301534071102062218518600215121929656196681258533477822665478
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_serr_address/latest/run.log
```
  UVM_FATAL @ 450626.0 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_serr_address_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000b4208
  UVM_INFO @ 450626.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_intr_wr_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 5 failures:

Test flash_ctrl_intr_wr has 2 failures.

0.flash_ctrl_intr_wr.31510877620327506316690496583587246018598090008796640475161110577202664062914
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_intr_wr/latest/run.log

  UVM_FATAL @ 45341.8 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_intr_wr_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00000800
  UVM_INFO @ 45341.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.flash_ctrl_intr_wr.55028163764929425275299926284545197559332653841734557865324951448786450568632
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_intr_wr/latest/run.log

  UVM_FATAL @ 8943.9 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_intr_wr_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00001cd0
  UVM_INFO @ 8943.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_intr_wr_slow_flash has 3 failures.

1.flash_ctrl_intr_wr_slow_flash.49232536757812761788480280840455148896454824834039665750924830598943596620419
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_intr_wr_slow_flash/latest/run.log

  UVM_FATAL @ 3044091.1 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_intr_wr_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00000fa0
  UVM_INFO @ 3044091.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.flash_ctrl_intr_wr_slow_flash.26217806605345391023924860707387912901913707602187798911781040632036867620606
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_intr_wr_slow_flash/latest/run.log

  UVM_FATAL @ 40346.2 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_intr_wr_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000008f0
  UVM_INFO @ 40346.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_derr_detect_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 4 failures:

Test flash_ctrl_derr_detect has 4 failures.

0.flash_ctrl_derr_detect.48072152549597339397292610903993191694862108068308636225984221613620979591000
Line 303, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_derr_detect/latest/run.log

  UVM_ERROR @ 143752.6 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_derr_detect_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 143752.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.flash_ctrl_derr_detect.21393889738179519849071376718586230032690604419789903074084989526235612198025
Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_derr_detect/latest/run.log

  UVM_ERROR @ 8528.1 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_derr_detect_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 8528.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_prog_reset_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 4 failures:
- Test flash_ctrl_prog_reset has 4 failures.
  - 1.flash_ctrl_prog_reset.84444903071518655019271827707980692657612379172833326028456609869317809474255
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_prog_reset/latest/run.log
```
  UVM_FATAL @ 107421.0 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_prog_reset_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00001760
  UVM_INFO @ 107421.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.flash_ctrl_prog_reset.44011585604246424359688192784520803196855389934306488931838404952593580061383
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_prog_reset/latest/run.log
```
  UVM_FATAL @ 26139.6 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_prog_reset_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00000fb8
  UVM_INFO @ 26139.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_common_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 3 failures:

Test flash_ctrl_sec_cm has 3 failures.

1.flash_ctrl_sec_cm.43355124858087684603181744692822979798215831119197433133391955285517411139368
Line 333, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_sec_cm/latest/run.log

  UVM_ERROR @ 11216.4 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 11216.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.flash_ctrl_sec_cm.45947001545569408630010787864938110390077472308326914323720634169635273498284
Line 331, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_sec_cm/latest/run.log

  UVM_ERROR @ 9537.6 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 9537.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_filesystem_support_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 3 failures:

Test flash_ctrl_fs_sup has 3 failures.

1.flash_ctrl_fs_sup.51711279749368100423758712788225671690930165547455503353539264042773359315201
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_fs_sup/latest/run.log

  UVM_FATAL @ 80768.7 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_filesystem_support_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00000d40
  UVM_INFO @ 80768.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.flash_ctrl_fs_sup.105698153426530685131738079191030873273403826919926580068349845760606507430257
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_fs_sup/latest/run.log

  UVM_FATAL @ 156848.5 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_filesystem_support_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00000ec8
  UVM_INFO @ 156848.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 3 failures:

Test flash_ctrl_rw_evict has 2 failures.

13.flash_ctrl_rw_evict.21940285709667232560257714023730397453708583686374830149658135755724805604413
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_rw_evict/latest/run.log

  UVM_FATAL @ 10860.8 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000152c8
  UVM_INFO @ 10860.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

26.flash_ctrl_rw_evict.105209543208540716302900865970849996206706756058922134508928521159439650080943
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/26.flash_ctrl_rw_evict/latest/run.log

  UVM_FATAL @ 9067.9 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00000968
  UVM_INFO @ 9067.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_rw_evict_all_en has 1 failures.

39.flash_ctrl_rw_evict_all_en.105890890668642315907313534959934862163492041873584085977442514143424842778318
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/39.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_FATAL @ 31614.2 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00001668
  UVM_INFO @ 31614.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 2 failures:

Test flash_ctrl_ro has 2 failures.

0.flash_ctrl_ro.7832249546715187302258220538790165955036617439150096455305745208700880580377
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_ro/latest/run.log

  UVM_ERROR @ 50839.0 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 50839.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.flash_ctrl_ro.89208714628768761476399559832523023771693732937587432700212097070188787585992
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_ro/latest/run.log

  UVM_ERROR @ 399896.0 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 399896.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout flash_ctrl_core_reg_block.op_status.done (addr=*) == * has 2 failures:
- Test flash_ctrl_oversize_error has 2 failures.
  - 0.flash_ctrl_oversize_error.78921598942780680328290626775979248530506886463996653888745211298725264635870
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_oversize_error/latest/run.log
```
  UVM_FATAL @ 10337314.4 ns: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout flash_ctrl_core_reg_block.op_status.done (addr=0x8d5cb170) == 0x1
  UVM_INFO @ 10337314.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.flash_ctrl_oversize_error.58189858759258989345956556560913249207797266853776074123593767905526924312607
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_oversize_error/latest/run.log
```
  UVM_FATAL @ 10018510.3 ns: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout flash_ctrl_core_reg_block.op_status.done (addr=0x7e0a6570) == 0x1
  UVM_INFO @ 10018510.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_oversize_error_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 2 failures:

Test flash_ctrl_oversize_error has 2 failures.

3.flash_ctrl_oversize_error.51949255953690586266352969421331953743392696330291961099597320996867909000635
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_oversize_error/latest/run.log

  UVM_ERROR @ 101375.8 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_oversize_error_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 101375.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.flash_ctrl_oversize_error.78155231361517974140277738220311273547852182370616628880307729780933383319262
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_oversize_error/latest/run.log

  UVM_ERROR @ 4807.7 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_oversize_error_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 4807.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_disable_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 2 failures:
- Test flash_ctrl_disable has 2 failures.
  - 22.flash_ctrl_disable.105429405676121457595972859882856749162735664778564401776531948103406972283467
    Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/22.flash_ctrl_disable/latest/run.log
```
  UVM_FATAL @ 9842.0 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_disable_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00001ee0
  UVM_INFO @ 9842.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 27.flash_ctrl_disable.12593290026363211029274151895137372232919463240815519308034517455374798118808
    Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/27.flash_ctrl_disable/latest/run.log
```
  UVM_FATAL @ 4757.6 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_disable_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00001538
  UVM_INFO @ 4757.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_base_vseq.sv:405) [flash_ctrl_write_word_sweep_vseq] Check failed (wd % * == *) prog_flash gets unexpected odd bus word count has 1 failures:
- Test flash_ctrl_write_word_sweep has 1 failures.
  - 0.flash_ctrl_write_word_sweep.105492636497051364393494608145872181839036239882377816809452650449496539422821
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_write_word_sweep/latest/run.log
```
  UVM_ERROR @ 90410.3 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_write_word_sweep_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 90410.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_base_vseq.sv:405) [flash_ctrl_common_vseq] Check failed (wd % * == *) prog_flash gets unexpected odd bus word count has 1 failures:
- Test flash_ctrl_sec_cm has 1 failures.
  - 0.flash_ctrl_sec_cm.18403799294135868332347162858532496549097774648310814092104588361467096677121
    Line 333, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_sec_cm/latest/run.log
```
  UVM_ERROR @ 22907.5 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 22907.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_access_after_disable_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 1 failures:
- Test flash_ctrl_access_after_disable has 1 failures.
  - 0.flash_ctrl_access_after_disable.10979448172054288023586835166125220508036467849112013713825679295786283666064
    Line 295, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_access_after_disable/latest/run.log
```
  UVM_FATAL @ 7169.2 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_access_after_disable_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00001648
  UVM_INFO @ 7169.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_base_vseq.sv:405) [flash_ctrl_derr_detect_vseq] Check failed (wd % * == *) prog_flash gets unexpected odd bus word count has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 1.flash_ctrl_derr_detect.70174245291904543264731938689599114614831598465199654413924125488542558292381
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 29433.6 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_derr_detect_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 29433.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_oversize_error_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 1 failures:
- Test flash_ctrl_oversize_error has 1 failures.
  - 1.flash_ctrl_oversize_error.11708623130537069792646918344166677094479894241748300548836261156097522715519
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_oversize_error/latest/run.log
```
  UVM_FATAL @ 74687.9 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_oversize_error_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00000928
  UVM_INFO @ 74687.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_access_after_disable_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 1 failures:
- Test flash_ctrl_access_after_disable has 1 failures.
  - 2.flash_ctrl_access_after_disable.23017945570960085654693175670677717652663067367647108808337031778265736024262
    Line 292, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_access_after_disable/latest/run.log
```
  UVM_ERROR @ 7305.0 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_access_after_disable_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 7305.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_common_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 1 failures:
- Test flash_ctrl_sec_cm has 1 failures.
  - 3.flash_ctrl_sec_cm.16432687907382093050470437455196618512852446449994764256569901220209142898567
    Line 298, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_sec_cm/latest/run.log
```
  UVM_FATAL @ 57021.6 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00001458
  UVM_INFO @ 57021.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending 'dst_req_o' has 1 failures:
- Test flash_ctrl_otp_reset has 1 failures.
  - 33.flash_ctrl_otp_reset.114733674216515847287024811173194507102849839518993732660498411093903553784315
    Line 387, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/33.flash_ctrl_otp_reset/latest/run.log
```
      Offending 'dst_req_o'
  UVM_ERROR @ 63682.1 ns: (prim_sync_reqack.sv:354) [ASSERT FAILED] SyncReqAckAckNeedsReq
  UVM_INFO @ 63682.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```