FLASH_CTRL Simulation Results

Wednesday November 22 2023 20:02:38 UTC

GitHub Revision: 4002b28ec4

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56541452733628775295814943325285397402671097056517970046183331126493552547969

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke flash_ctrl_smoke 1.235m 54.148us 50 50 100.00
V1 smoke_hw flash_ctrl_smoke_hw 23.900s 27.192us 5 5 100.00
V1 csr_hw_reset flash_ctrl_csr_hw_reset 38.250s 90.798us 5 5 100.00
V1 csr_rw flash_ctrl_csr_rw 14.970s 120.230us 20 20 100.00
V1 csr_bit_bash flash_ctrl_csr_bit_bash 1.299m 5.710ms 5 5 100.00
V1 csr_aliasing flash_ctrl_csr_aliasing 59.140s 2.932ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset flash_ctrl_csr_mem_rw_with_rand_reset 15.630s 80.564us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr flash_ctrl_csr_rw 14.970s 120.230us 20 20 100.00
flash_ctrl_csr_aliasing 59.140s 2.932ms 5 5 100.00
V1 mem_walk flash_ctrl_mem_walk 13.620s 24.820us 5 5 100.00
V1 mem_partial_access flash_ctrl_mem_partial_access 13.670s 26.547us 5 5 100.00
V1 TOTAL 120 120 100.00
V2 sw_op flash_ctrl_sw_op 23.900s 51.111us 5 5 100.00
V2 host_read_direct flash_ctrl_host_dir_rd 2.039m 133.105us 5 5 100.00
V2 rma_hw_if flash_ctrl_hw_rma 27.173m 170.174ms 3 3 100.00
flash_ctrl_hw_rma_reset 13.035m 80.145ms 20 20 100.00
flash_ctrl_lcmgr_intg 13.790s 26.692us 20 20 100.00
V2 host_controller_arb flash_ctrl_host_ctrl_arb 33.962m 339.772ms 5 5 100.00
V2 erase_suspend flash_ctrl_erase_suspend 7.485m 5.615ms 5 5 100.00
V2 program_reset flash_ctrl_prog_reset 15.150s 68.958us 30 30 100.00
V2 full_memory_access flash_ctrl_full_mem_access 40.313m 179.796ms 5 5 100.00
V2 rd_buff_eviction flash_ctrl_rd_buff_evict 1.661m 158.315us 5 5 100.00
V2 rd_buff_eviction_w_ecc flash_ctrl_rw_evict 33.430s 160.228us 40 40 100.00
flash_ctrl_rw_evict_all_en 29.810s 53.067us 40 40 100.00
flash_ctrl_re_evict 37.130s 290.374us 20 20 100.00
V2 host_arb flash_ctrl_phy_arb 9.287m 2.896ms 20 20 100.00
V2 host_interleave flash_ctrl_phy_arb 9.287m 2.896ms 20 20 100.00
V2 memory_protection flash_ctrl_mp_regions 2.416m 10.404ms 20 20 100.00
V2 fetch_code flash_ctrl_fetch_code 21.480s 689.713us 10 10 100.00
V2 all_partitions flash_ctrl_rand_ops 13.291m 348.468us 20 20 100.00
V2 error_mp flash_ctrl_error_mp 36.356m 8.290ms 10 10 100.00
V2 error_prog_win flash_ctrl_error_prog_win 14.896m 1.611ms 10 10 100.00
V2 error_prog_type flash_ctrl_error_prog_type 38.906m 1.721ms 5 5 100.00
V2 error_read_seed flash_ctrl_hw_read_seed_err 13.640s 26.796us 20 20 100.00
V2 read_write_overflow flash_ctrl_oversize_error 2.794m 2.377ms 5 5 100.00
V2 flash_ctrl_disable flash_ctrl_disable 22.250s 21.409us 50 50 100.00
V2 flash_ctrl_connect flash_ctrl_connect 13.580s 23.032us 80 80 100.00
V2 stress_all flash_ctrl_stress_all 24.160m 660.967us 5 5 100.00
V2 secret_partition flash_ctrl_hw_sec_otp 2.261m 9.221ms 50 50 100.00
flash_ctrl_otp_reset 1.924m 83.164us 80 80 100.00
V2 isolation_partition flash_ctrl_hw_rma 27.173m 170.174ms 3 3 100.00
V2 interrupts flash_ctrl_intr_rd 2.623m 2.253ms 40 40 100.00
flash_ctrl_intr_wr 1.492m 7.932ms 10 10 100.00
flash_ctrl_intr_rd_slow_flash 3.622m 16.816ms 40 40 100.00
flash_ctrl_intr_wr_slow_flash 5.350m 79.793ms 10 10 100.00
V2 invalid_op flash_ctrl_invalid_op 1.010m 3.951ms 20 20 100.00
V2 mid_op_rst flash_ctrl_mid_op_rst 1.160m 1.869ms 5 5 100.00
V2 double_bit_err flash_ctrl_read_word_sweep_derr 22.610s 34.222us 5 5 100.00
flash_ctrl_ro_derr 2.198m 1.210ms 10 10 100.00
flash_ctrl_rw_derr 9.279m 7.356ms 10 10 100.00
flash_ctrl_derr_detect 1.735m 186.166us 5 5 100.00
flash_ctrl_integrity 9.893m 7.098ms 5 5 100.00
V2 single_bit_err flash_ctrl_read_word_sweep_serr 22.410s 44.809us 5 5 100.00
flash_ctrl_ro_serr 2.136m 1.215ms 10 10 100.00
flash_ctrl_rw_serr 9.611m 7.233ms 10 10 100.00
V2 singlebit_err_counter flash_ctrl_serr_counter 1.130m 1.362ms 5 5 100.00
V2 singlebit_err_address flash_ctrl_serr_address 1.333m 1.782ms 5 5 100.00
V2 scramble flash_ctrl_wo 2.454m 4.091ms 20 20 100.00
flash_ctrl_write_word_sweep 16.440s 125.555us 1 1 100.00
flash_ctrl_read_word_sweep 14.010s 48.678us 1 1 100.00
flash_ctrl_ro 1.715m 862.020us 20 20 100.00
flash_ctrl_rw 8.154m 6.890ms 20 20 100.00
V2 filesystem_support flash_ctrl_fs_sup 33.870s 637.110us 5 5 100.00
V2 rma_write_process_error flash_ctrl_rma_err 13.786m 86.990ms 3 3 100.00
flash_ctrl_hw_prog_rma_wipe_err 1.243m 10.019ms 20 20 100.00
V2 alert_test flash_ctrl_alert_test 14.200s 87.990us 50 50 100.00
V2 intr_test flash_ctrl_intr_test 13.860s 28.044us 50 50 100.00
V2 tl_d_oob_addr_access flash_ctrl_tl_errors 19.070s 100.678us 20 20 100.00
V2 tl_d_illegal_access flash_ctrl_tl_errors 19.070s 100.678us 20 20 100.00
V2 tl_d_outstanding_access flash_ctrl_csr_hw_reset 38.250s 90.798us 5 5 100.00
flash_ctrl_csr_rw 14.970s 120.230us 20 20 100.00
flash_ctrl_csr_aliasing 59.140s 2.932ms 5 5 100.00
flash_ctrl_same_csr_outstanding 18.050s 363.902us 20 20 100.00
V2 tl_d_partial_access flash_ctrl_csr_hw_reset 38.250s 90.798us 5 5 100.00
flash_ctrl_csr_rw 14.970s 120.230us 20 20 100.00
flash_ctrl_csr_aliasing 59.140s 2.932ms 5 5 100.00
flash_ctrl_same_csr_outstanding 18.050s 363.902us 20 20 100.00
V2 TOTAL 1013 1013 100.00
V2S shadow_reg_update_error flash_ctrl_shadow_reg_errors 13.430s 19.225us 20 20 100.00
V2S shadow_reg_read_clear_staged_value flash_ctrl_shadow_reg_errors 13.430s 19.225us 20 20 100.00
V2S shadow_reg_storage_error flash_ctrl_shadow_reg_errors 13.430s 19.225us 20 20 100.00
V2S shadowed_reset_glitch flash_ctrl_shadow_reg_errors 13.430s 19.225us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw flash_ctrl_shadow_reg_errors_with_csr_rw 13.550s 19.225us 20 20 100.00
V2S tl_intg_err flash_ctrl_sec_cm 1.313h 2.976ms 5 5 100.00
flash_ctrl_tl_intg_err 12.661m 1.497ms 20 20 100.00
V2S sec_cm_reg_bus_integrity flash_ctrl_tl_intg_err 12.661m 1.497ms 20 20 100.00
V2S sec_cm_host_bus_integrity flash_ctrl_tl_intg_err 12.661m 1.497ms 20 20 100.00
V2S sec_cm_mem_bus_integrity flash_ctrl_rd_intg 29.090s 122.289us 3 3 100.00
flash_ctrl_wr_intg 14.710s 86.305us 3 3 100.00
V2S sec_cm_scramble_key_sideload flash_ctrl_smoke 1.235m 54.148us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi flash_ctrl_otp_reset 1.924m 83.164us 80 80 100.00
flash_ctrl_disable 22.250s 21.409us 50 50 100.00
flash_ctrl_sec_info_access 1.216m 3.550ms 50 50 100.00
flash_ctrl_connect 13.580s 23.032us 80 80 100.00
V2S sec_cm_ctrl_config_regwen flash_ctrl_config_regwen 13.700s 33.847us 5 5 100.00
V2S sec_cm_data_regions_config_regwen flash_ctrl_csr_rw 14.970s 120.230us 20 20 100.00
V2S sec_cm_data_regions_config_shadow flash_ctrl_shadow_reg_errors 13.430s 19.225us 20 20 100.00
V2S sec_cm_info_regions_config_regwen flash_ctrl_csr_rw 14.970s 120.230us 20 20 100.00
V2S sec_cm_info_regions_config_shadow flash_ctrl_shadow_reg_errors 13.430s 19.225us 20 20 100.00
V2S sec_cm_bank_config_regwen flash_ctrl_csr_rw 14.970s 120.230us 20 20 100.00
V2S sec_cm_bank_config_shadow flash_ctrl_shadow_reg_errors 13.430s 19.225us 20 20 100.00
V2S sec_cm_mem_ctrl_global_esc flash_ctrl_disable 22.250s 21.409us 50 50 100.00
V2S sec_cm_mem_ctrl_local_esc flash_ctrl_rd_intg 29.090s 122.289us 3 3 100.00
flash_ctrl_access_after_disable 13.500s 22.512us 3 3 100.00
V2S sec_cm_mem_disable_config_mubi flash_ctrl_disable 22.250s 21.409us 50 50 100.00
V2S sec_cm_exec_config_redun flash_ctrl_fetch_code 21.480s 689.713us 10 10 100.00
V2S sec_cm_mem_scramble flash_ctrl_rw 8.154m 6.890ms 20 20 100.00
V2S sec_cm_mem_integrity flash_ctrl_rw_serr 9.611m 7.233ms 10 10 100.00
flash_ctrl_rw_derr 9.279m 7.356ms 10 10 100.00
flash_ctrl_integrity 9.893m 7.098ms 5 5 100.00
V2S sec_cm_rma_entry_mem_sec_wipe flash_ctrl_hw_rma 27.173m 170.174ms 3 3 100.00
V2S sec_cm_ctrl_fsm_sparse flash_ctrl_sec_cm 1.313h 2.976ms 5 5 100.00
V2S sec_cm_phy_fsm_sparse flash_ctrl_sec_cm 1.313h 2.976ms 5 5 100.00
V2S sec_cm_phy_prog_fsm_sparse flash_ctrl_sec_cm 1.313h 2.976ms 5 5 100.00
V2S sec_cm_ctr_redun flash_ctrl_sec_cm 1.313h 2.976ms 5 5 100.00
V2S sec_cm_phy_arbiter_ctrl_redun flash_ctrl_phy_arb_redun 16.430s 94.729us 5 5 100.00
V2S sec_cm_phy_host_grant_ctrl_consistency flash_ctrl_phy_host_grant_err 13.850s 25.236us 5 5 100.00
V2S sec_cm_phy_ack_ctrl_consistency flash_ctrl_phy_ack_consistency 14.010s 24.883us 5 5 100.00
V2S sec_cm_fifo_ctr_redun flash_ctrl_sec_cm 1.313h 2.976ms 5 5 100.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse flash_ctrl_sec_cm 1.313h 2.976ms 5 5 100.00
V2S sec_cm_prog_tl_lc_gate_fsm_sparse flash_ctrl_sec_cm 1.313h 2.976ms 5 5 100.00
V2S TOTAL 144 144 100.00
V3 asymmetric_read_path flash_ctrl_rd_ooo 48.370s 207.652us 1 1 100.00
V3 stress_all_with_rand_reset flash_ctrl_stress_all_with_rand_reset 0 0 --
V3 TOTAL 1 1 100.00
TOTAL 1278 1278 100.00

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 55 55 55 100.00
V2S 12 12 12 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
94.60 95.23 92.65 97.77 85.71 97.01 98.30 95.56

Past Results