Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	23646001	1		T15	56		T44	273		T45	846
full_word	7919639	1		T15	1		T44	84		T45	253

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	31565350	1		T15	57		T44	357		T45	1099
auto[TlIntgErrCmd]	95	1		T49	3		T55	4		T56	2
auto[TlIntgErrData]	100	1		T49	3		T55	10		T56	4
auto[TlIntgErrBoth]	95	1		T49	4		T55	6		T56	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	27120058	1		T15	57		T44	254		T45	151
auto[1]	4445582	1		T44	103		T45	948		T46	103

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	23025150	1		T15	56		T44	230		T45	108
auto[TlIntgErrNone]	partial	auto[1]	620592	1		T44	43		T45	738		T46	47
auto[TlIntgErrNone]	full_word	auto[0]	4094781	1		T15	1		T44	24		T45	43
auto[TlIntgErrNone]	full_word	auto[1]	3824827	1		T44	60		T45	210		T46	56
auto[TlIntgErrCmd]	partial	auto[0]	37	1		T55	1		T56	1		T237	1
auto[TlIntgErrCmd]	partial	auto[1]	48	1		T49	3		T55	3		T56	1
auto[TlIntgErrCmd]	full_word	auto[0]	5	1		T238	1		T321	1		T316	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T237	1		T322	1		T265	1
auto[TlIntgErrData]	partial	auto[0]	36	1		T49	1		T55	5		T56	1
auto[TlIntgErrData]	partial	auto[1]	52	1		T49	2		T55	5		T56	2
auto[TlIntgErrData]	full_word	auto[0]	8	1		T56	1		T317	1		T315	2
auto[TlIntgErrData]	full_word	auto[1]	4	1		T265	1		T316	1		T320	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1		T49	1		T55	2		T237	2
auto[TlIntgErrBoth]	partial	auto[1]	51	1		T49	2		T55	3		T56	4
auto[TlIntgErrBoth]	full_word	auto[0]	6	1		T49	1		T55	1		T295	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T259	1		T316	1		T323	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	21976	1		T45	381		T49	8		T116	473
full_word	4469914	1		T45	324		T49	1		T116	341

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4491631	1		T45	705		T116	814		T118	971
auto[TlIntgErrCmd]	86	1		T49	5		T55	9		T56	3
auto[TlIntgErrData]	78	1		T49	2		T55	4		T56	3
auto[TlIntgErrBoth]	95	1		T49	2		T55	4		T56	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4462934	1		T45	34		T49	4		T116	49
auto[1]	28956	1		T45	671		T49	5		T116	765

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1363	1		T45	31		T116	37		T118	29
auto[TlIntgErrNone]	partial	auto[1]	20381	1		T45	350		T116	436		T118	782
auto[TlIntgErrNone]	full_word	auto[0]	4461464	1		T45	3		T116	12		T118	2
auto[TlIntgErrNone]	full_word	auto[1]	8423	1		T45	321		T116	329		T118	158
auto[TlIntgErrCmd]	partial	auto[0]	26	1		T49	1		T55	3		T56	1
auto[TlIntgErrCmd]	partial	auto[1]	54	1		T49	3		T55	5		T56	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1		T49	1		T55	1		T315	2
auto[TlIntgErrCmd]	full_word	auto[1]	1	1		T318	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	38	1		T49	2		T55	3		T56	1
auto[TlIntgErrData]	partial	auto[1]	30	1		T55	1		T56	2		T237	3
auto[TlIntgErrData]	full_word	auto[0]	5	1		T238	1		T317	1		T318	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T237	1		T258	1		T318	1
auto[TlIntgErrBoth]	partial	auto[0]	28	1		T55	1		T56	1		T237	1
auto[TlIntgErrBoth]	partial	auto[1]	56	1		T49	2		T55	3		T56	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T317	1		T324	1		T316	2
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T56	1		T295	1		T259	1