Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T7

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1705765352	1702538196	0	0
CheckNGreaterZero_A	4240	4240	0	0
GntImpliesReady_A	1705765352	448789455	0	0
GntImpliesValid_A	1705765352	448789455	0	0
GrantKnown_A	1705765352	1702538196	0	0
IdxKnown_A	1705765352	1702538196	0	0
IndexIsCorrect_A	1705765352	448789455	0	0
NoReadyValidNoGrant_A	1705765352	180165862	0	0
Priority_A	1705765352	473352095	0	0
ReadyAndValidImplyGrant_A	1705765352	448789455	0	0
ReqAndReadyImplyGrant_A	1705765352	448789455	0	0
ReqImpliesValid_A	1705765352	473352095	0	0
ValidKnown_A	1705765352	1702538196	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1705765352	1702538196	0	0
T1	8540	8340	0	0
T2	3539056	3538468	0	0
T3	4692	4480	0	0
T4	388476	387792	0	0
T5	315052	314688	0	0
T6	839608	839292	0	0
T7	3274332	3273816	0	0
T12	971060	971056	0	0
T20	6072	5720	0	0
T21	1005668	1005464	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4240	4240	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T12	4	4	0	0
T20	4	4	0	0
T21	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1705765352	448789455	0	0
T1	4270	64	0	0
T2	3539056	63156	0	0
T3	4692	64	0	0
T4	388476	62286	0	0
T5	315052	85512	0	0
T6	839608	89198	0	0
T7	3274332	58274	0	0
T8	84524	0	0	0
T12	971060	1662456	0	0
T20	6072	98	0	0
T21	1005668	463634	0	0
T22	0	1690	0	0
T25	0	26	0	0
T34	0	11462	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1705765352	448789455	0	0
T1	4270	64	0	0
T2	3539056	63156	0	0
T3	4692	64	0	0
T4	388476	62286	0	0
T5	315052	85512	0	0
T6	839608	89198	0	0
T7	3274332	58274	0	0
T8	84524	0	0	0
T12	971060	1662456	0	0
T20	6072	98	0	0
T21	1005668	463634	0	0
T22	0	1690	0	0
T25	0	26	0	0
T34	0	11462	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1705765352	1702538196	0	0
T1	8540	8340	0	0
T2	3539056	3538468	0	0
T3	4692	4480	0	0
T4	388476	387792	0	0
T5	315052	314688	0	0
T6	839608	839292	0	0
T7	3274332	3273816	0	0
T12	971060	971056	0	0
T20	6072	5720	0	0
T21	1005668	1005464	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1705765352	1702538196	0	0
T1	8540	8340	0	0
T2	3539056	3538468	0	0
T3	4692	4480	0	0
T4	388476	387792	0	0
T5	315052	314688	0	0
T6	839608	839292	0	0
T7	3274332	3273816	0	0
T12	971060	971056	0	0
T20	6072	5720	0	0
T21	1005668	1005464	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1705765352	448789455	0	0
T1	4270	64	0	0
T2	3539056	63156	0	0
T3	4692	64	0	0
T4	388476	62286	0	0
T5	315052	85512	0	0
T6	839608	89198	0	0
T7	3274332	58274	0	0
T8	84524	0	0	0
T12	971060	1662456	0	0
T20	6072	98	0	0
T21	1005668	463634	0	0
T22	0	1690	0	0
T25	0	26	0	0
T34	0	11462	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1705765352	180165862	0	0
T1	4270	256	0	0
T2	3539056	2077700	0	0
T3	4692	256	0	0
T4	388476	102442	0	0
T5	315052	128	0	0
T6	839608	7492	0	0
T7	3274332	1921940	0	0
T8	84524	0	0	0
T12	971060	2109974	0	0
T20	6072	308	0	0
T21	1005668	256	0	0
T22	0	256	0	0
T25	0	40	0	0
T26	0	88898	0	0
T34	0	1578	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1705765352	473352095	0	0
T1	4270	64	0	0
T2	3539056	548588	0	0
T3	4692	64	0	0
T4	388476	72434	0	0
T5	315052	85512	0	0
T6	839608	89198	0	0
T7	3274332	534218	0	0
T8	84524	0	0	0
T12	971060	1662456	0	0
T20	6072	98	0	0
T21	1005668	463634	0	0
T22	0	1690	0	0
T25	0	26	0	0
T34	0	11462	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1705765352	448789455	0	0
T1	4270	64	0	0
T2	3539056	63156	0	0
T3	4692	64	0	0
T4	388476	62286	0	0
T5	315052	85512	0	0
T6	839608	89198	0	0
T7	3274332	58274	0	0
T8	84524	0	0	0
T12	971060	1662456	0	0
T20	6072	98	0	0
T21	1005668	463634	0	0
T22	0	1690	0	0
T25	0	26	0	0
T34	0	11462	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1705765352	448789455	0	0
T1	4270	64	0	0
T2	3539056	63156	0	0
T3	4692	64	0	0
T4	388476	62286	0	0
T5	315052	85512	0	0
T6	839608	89198	0	0
T7	3274332	58274	0	0
T8	84524	0	0	0
T12	971060	1662456	0	0
T20	6072	98	0	0
T21	1005668	463634	0	0
T22	0	1690	0	0
T25	0	26	0	0
T34	0	11462	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1705765352	473352095	0	0
T1	4270	64	0	0
T2	3539056	548588	0	0
T3	4692	64	0	0
T4	388476	72434	0	0
T5	315052	85512	0	0
T6	839608	89198	0	0
T7	3274332	534218	0	0
T8	84524	0	0	0
T12	971060	1662456	0	0
T20	6072	98	0	0
T21	1005668	463634	0	0
T22	0	1690	0	0
T25	0	26	0	0
T34	0	11462	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1705765352	1702538196	0	0
T1	8540	8340	0	0
T2	3539056	3538468	0	0
T3	4692	4480	0	0
T4	388476	387792	0	0
T5	315052	314688	0	0
T6	839608	839292	0	0
T7	3274332	3273816	0	0
T12	971060	971056	0	0
T20	6072	5720	0	0
T21	1005668	1005464	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426441338	425634549	0	0
CheckNGreaterZero_A	1060	1060	0	0
GntImpliesReady_A	426441338	124989416	0	0
GntImpliesValid_A	426441338	124989416	0	0
GrantKnown_A	426441338	425634549	0	0
IdxKnown_A	426441338	425634549	0	0
IndexIsCorrect_A	426441338	124989416	0	0
NoReadyValidNoGrant_A	426441338	47318112	0	0
Priority_A	426441338	131237160	0	0
ReadyAndValidImplyGrant_A	426441338	124989416	0	0
ReqAndReadyImplyGrant_A	426441338	124989416	0	0
ReqImpliesValid_A	426441338	131237160	0	0
ValidKnown_A	426441338	425634549	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	425634549	0	0
T1	2135	2085	0	0
T2	884764	884617	0	0
T3	1173	1120	0	0
T4	97119	96948	0	0
T5	78763	78672	0	0
T6	209902	209823	0	0
T7	818583	818454	0	0
T12	242765	242764	0	0
T20	1518	1430	0	0
T21	251417	251366	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	124989416	0	0
T1	2135	32	0	0
T2	884764	15458	0	0
T3	1173	32	0	0
T4	97119	16360	0	0
T5	78763	42756	0	0
T6	209902	23956	0	0
T7	818583	14223	0	0
T12	242765	417971	0	0
T20	1518	32	0	0
T21	251417	121108	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	124989416	0	0
T1	2135	32	0	0
T2	884764	15458	0	0
T3	1173	32	0	0
T4	97119	16360	0	0
T5	78763	42756	0	0
T6	209902	23956	0	0
T7	818583	14223	0	0
T12	242765	417971	0	0
T20	1518	32	0	0
T21	251417	121108	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	425634549	0	0
T1	2135	2085	0	0
T2	884764	884617	0	0
T3	1173	1120	0	0
T4	97119	96948	0	0
T5	78763	78672	0	0
T6	209902	209823	0	0
T7	818583	818454	0	0
T12	242765	242764	0	0
T20	1518	1430	0	0
T21	251417	251366	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	425634549	0	0
T1	2135	2085	0	0
T2	884764	884617	0	0
T3	1173	1120	0	0
T4	97119	96948	0	0
T5	78763	78672	0	0
T6	209902	209823	0	0
T7	818583	818454	0	0
T12	242765	242764	0	0
T20	1518	1430	0	0
T21	251417	251366	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	124989416	0	0
T1	2135	32	0	0
T2	884764	15458	0	0
T3	1173	32	0	0
T4	97119	16360	0	0
T5	78763	42756	0	0
T6	209902	23956	0	0
T7	818583	14223	0	0
T12	242765	417971	0	0
T20	1518	32	0	0
T21	251417	121108	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	47318112	0	0
T1	2135	128	0	0
T2	884764	518862	0	0
T3	1173	128	0	0
T4	97119	29682	0	0
T5	78763	64	0	0
T6	209902	2060	0	0
T7	818583	474881	0	0
T12	242765	530662	0	0
T20	1518	128	0	0
T21	251417	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	131237160	0	0
T1	2135	32	0	0
T2	884764	108875	0	0
T3	1173	32	0	0
T4	97119	18640	0	0
T5	78763	42756	0	0
T6	209902	23956	0	0
T7	818583	134093	0	0
T12	242765	417971	0	0
T20	1518	32	0	0
T21	251417	121108	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	124989416	0	0
T1	2135	32	0	0
T2	884764	15458	0	0
T3	1173	32	0	0
T4	97119	16360	0	0
T5	78763	42756	0	0
T6	209902	23956	0	0
T7	818583	14223	0	0
T12	242765	417971	0	0
T20	1518	32	0	0
T21	251417	121108	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	124989416	0	0
T1	2135	32	0	0
T2	884764	15458	0	0
T3	1173	32	0	0
T4	97119	16360	0	0
T5	78763	42756	0	0
T6	209902	23956	0	0
T7	818583	14223	0	0
T12	242765	417971	0	0
T20	1518	32	0	0
T21	251417	121108	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	131237160	0	0
T1	2135	32	0	0
T2	884764	108875	0	0
T3	1173	32	0	0
T4	97119	18640	0	0
T5	78763	42756	0	0
T6	209902	23956	0	0
T7	818583	134093	0	0
T12	242765	417971	0	0
T20	1518	32	0	0
T21	251417	121108	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	425634549	0	0
T1	2135	2085	0	0
T2	884764	884617	0	0
T3	1173	1120	0	0
T4	97119	96948	0	0
T5	78763	78672	0	0
T6	209902	209823	0	0
T7	818583	818454	0	0
T12	242765	242764	0	0
T20	1518	1430	0	0
T21	251417	251366	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426441338	425634549	0	0
CheckNGreaterZero_A	1060	1060	0	0
GntImpliesReady_A	426441338	124974773	0	0
GntImpliesValid_A	426441338	124974773	0	0
GrantKnown_A	426441338	425634549	0	0
IdxKnown_A	426441338	425634549	0	0
IndexIsCorrect_A	426441338	124974773	0	0
NoReadyValidNoGrant_A	426441338	47318112	0	0
Priority_A	426441338	131222517	0	0
ReadyAndValidImplyGrant_A	426441338	124974773	0	0
ReqAndReadyImplyGrant_A	426441338	124974773	0	0
ReqImpliesValid_A	426441338	131222517	0	0
ValidKnown_A	426441338	425634549	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	425634549	0	0
T1	2135	2085	0	0
T2	884764	884617	0	0
T3	1173	1120	0	0
T4	97119	96948	0	0
T5	78763	78672	0	0
T6	209902	209823	0	0
T7	818583	818454	0	0
T12	242765	242764	0	0
T20	1518	1430	0	0
T21	251417	251366	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	124974773	0	0
T1	2135	32	0	0
T2	884764	15458	0	0
T3	1173	32	0	0
T4	97119	16360	0	0
T5	78763	42756	0	0
T6	209902	23956	0	0
T7	818583	14223	0	0
T12	242765	417971	0	0
T20	1518	32	0	0
T21	251417	121108	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	124974773	0	0
T1	2135	32	0	0
T2	884764	15458	0	0
T3	1173	32	0	0
T4	97119	16360	0	0
T5	78763	42756	0	0
T6	209902	23956	0	0
T7	818583	14223	0	0
T12	242765	417971	0	0
T20	1518	32	0	0
T21	251417	121108	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	425634549	0	0
T1	2135	2085	0	0
T2	884764	884617	0	0
T3	1173	1120	0	0
T4	97119	96948	0	0
T5	78763	78672	0	0
T6	209902	209823	0	0
T7	818583	818454	0	0
T12	242765	242764	0	0
T20	1518	1430	0	0
T21	251417	251366	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	425634549	0	0
T1	2135	2085	0	0
T2	884764	884617	0	0
T3	1173	1120	0	0
T4	97119	96948	0	0
T5	78763	78672	0	0
T6	209902	209823	0	0
T7	818583	818454	0	0
T12	242765	242764	0	0
T20	1518	1430	0	0
T21	251417	251366	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	124974773	0	0
T1	2135	32	0	0
T2	884764	15458	0	0
T3	1173	32	0	0
T4	97119	16360	0	0
T5	78763	42756	0	0
T6	209902	23956	0	0
T7	818583	14223	0	0
T12	242765	417971	0	0
T20	1518	32	0	0
T21	251417	121108	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	47318112	0	0
T1	2135	128	0	0
T2	884764	518862	0	0
T3	1173	128	0	0
T4	97119	29682	0	0
T5	78763	64	0	0
T6	209902	2060	0	0
T7	818583	474881	0	0
T12	242765	530662	0	0
T20	1518	128	0	0
T21	251417	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	131222517	0	0
T1	2135	32	0	0
T2	884764	108875	0	0
T3	1173	32	0	0
T4	97119	18640	0	0
T5	78763	42756	0	0
T6	209902	23956	0	0
T7	818583	134093	0	0
T12	242765	417971	0	0
T20	1518	32	0	0
T21	251417	121108	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	124974773	0	0
T1	2135	32	0	0
T2	884764	15458	0	0
T3	1173	32	0	0
T4	97119	16360	0	0
T5	78763	42756	0	0
T6	209902	23956	0	0
T7	818583	14223	0	0
T12	242765	417971	0	0
T20	1518	32	0	0
T21	251417	121108	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	124974773	0	0
T1	2135	32	0	0
T2	884764	15458	0	0
T3	1173	32	0	0
T4	97119	16360	0	0
T5	78763	42756	0	0
T6	209902	23956	0	0
T7	818583	14223	0	0
T12	242765	417971	0	0
T20	1518	32	0	0
T21	251417	121108	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	131222517	0	0
T1	2135	32	0	0
T2	884764	108875	0	0
T3	1173	32	0	0
T4	97119	18640	0	0
T5	78763	42756	0	0
T6	209902	23956	0	0
T7	818583	134093	0	0
T12	242765	417971	0	0
T20	1518	32	0	0
T21	251417	121108	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	425634549	0	0
T1	2135	2085	0	0
T2	884764	884617	0	0
T3	1173	1120	0	0
T4	97119	96948	0	0
T5	78763	78672	0	0
T6	209902	209823	0	0
T7	818583	818454	0	0
T12	242765	242764	0	0
T20	1518	1430	0	0
T21	251417	251366	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T20
1	0	Covered	T2,T4,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T2,T4,T20
1	1	Covered	T2,T4,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T2,T4,T20

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T2,T4,T20

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426441338	425634549	0	0
CheckNGreaterZero_A	1060	1060	0	0
GntImpliesReady_A	426441338	99412633	0	0
GntImpliesValid_A	426441338	99412633	0	0
GrantKnown_A	426441338	425634549	0	0
IdxKnown_A	426441338	425634549	0	0
IndexIsCorrect_A	426441338	99412633	0	0
NoReadyValidNoGrant_A	426441338	42764819	0	0
Priority_A	426441338	105446209	0	0
ReadyAndValidImplyGrant_A	426441338	99412633	0	0
ReqAndReadyImplyGrant_A	426441338	99412633	0	0
ReqImpliesValid_A	426441338	105446209	0	0
ValidKnown_A	426441338	425634549	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	425634549	0	0
T1	2135	2085	0	0
T2	884764	884617	0	0
T3	1173	1120	0	0
T4	97119	96948	0	0
T5	78763	78672	0	0
T6	209902	209823	0	0
T7	818583	818454	0	0
T12	242765	242764	0	0
T20	1518	1430	0	0
T21	251417	251366	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	99412633	0	0
T2	884764	16120	0	0
T3	1173	0	0	0
T4	97119	14783	0	0
T5	78763	0	0	0
T6	209902	20643	0	0
T7	818583	14914	0	0
T8	42262	0	0	0
T12	242765	413257	0	0
T20	1518	17	0	0
T21	251417	110709	0	0
T22	0	845	0	0
T25	0	13	0	0
T34	0	5731	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	99412633	0	0
T2	884764	16120	0	0
T3	1173	0	0	0
T4	97119	14783	0	0
T5	78763	0	0	0
T6	209902	20643	0	0
T7	818583	14914	0	0
T8	42262	0	0	0
T12	242765	413257	0	0
T20	1518	17	0	0
T21	251417	110709	0	0
T22	0	845	0	0
T25	0	13	0	0
T34	0	5731	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	425634549	0	0
T1	2135	2085	0	0
T2	884764	884617	0	0
T3	1173	1120	0	0
T4	97119	96948	0	0
T5	78763	78672	0	0
T6	209902	209823	0	0
T7	818583	818454	0	0
T12	242765	242764	0	0
T20	1518	1430	0	0
T21	251417	251366	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	425634549	0	0
T1	2135	2085	0	0
T2	884764	884617	0	0
T3	1173	1120	0	0
T4	97119	96948	0	0
T5	78763	78672	0	0
T6	209902	209823	0	0
T7	818583	818454	0	0
T12	242765	242764	0	0
T20	1518	1430	0	0
T21	251417	251366	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	99412633	0	0
T2	884764	16120	0	0
T3	1173	0	0	0
T4	97119	14783	0	0
T5	78763	0	0	0
T6	209902	20643	0	0
T7	818583	14914	0	0
T8	42262	0	0	0
T12	242765	413257	0	0
T20	1518	17	0	0
T21	251417	110709	0	0
T22	0	845	0	0
T25	0	13	0	0
T34	0	5731	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	42764819	0	0
T2	884764	519988	0	0
T3	1173	0	0	0
T4	97119	21539	0	0
T5	78763	0	0	0
T6	209902	1686	0	0
T7	818583	486089	0	0
T8	42262	0	0	0
T12	242765	524325	0	0
T20	1518	26	0	0
T21	251417	0	0	0
T22	0	128	0	0
T25	0	20	0	0
T26	0	44449	0	0
T34	0	789	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	105446209	0	0
T2	884764	165419	0	0
T3	1173	0	0	0
T4	97119	17577	0	0
T5	78763	0	0	0
T6	209902	20643	0	0
T7	818583	133016	0	0
T8	42262	0	0	0
T12	242765	413257	0	0
T20	1518	17	0	0
T21	251417	110709	0	0
T22	0	845	0	0
T25	0	13	0	0
T34	0	5731	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	99412633	0	0
T2	884764	16120	0	0
T3	1173	0	0	0
T4	97119	14783	0	0
T5	78763	0	0	0
T6	209902	20643	0	0
T7	818583	14914	0	0
T8	42262	0	0	0
T12	242765	413257	0	0
T20	1518	17	0	0
T21	251417	110709	0	0
T22	0	845	0	0
T25	0	13	0	0
T34	0	5731	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	99412633	0	0
T2	884764	16120	0	0
T3	1173	0	0	0
T4	97119	14783	0	0
T5	78763	0	0	0
T6	209902	20643	0	0
T7	818583	14914	0	0
T8	42262	0	0	0
T12	242765	413257	0	0
T20	1518	17	0	0
T21	251417	110709	0	0
T22	0	845	0	0
T25	0	13	0	0
T34	0	5731	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	105446209	0	0
T2	884764	165419	0	0
T3	1173	0	0	0
T4	97119	17577	0	0
T5	78763	0	0	0
T6	209902	20643	0	0
T7	818583	133016	0	0
T8	42262	0	0	0
T12	242765	413257	0	0
T20	1518	17	0	0
T21	251417	110709	0	0
T22	0	845	0	0
T25	0	13	0	0
T34	0	5731	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	425634549	0	0
T1	2135	2085	0	0
T2	884764	884617	0	0
T3	1173	1120	0	0
T4	97119	96948	0	0
T5	78763	78672	0	0
T6	209902	209823	0	0
T7	818583	818454	0	0
T12	242765	242764	0	0
T20	1518	1430	0	0
T21	251417	251366	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T20
1	0	Covered	T2,T4,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T2,T4,T20
1	1	Covered	T2,T4,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T2,T4,T20

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T2,T4,T20

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426441338	425634549	0	0
CheckNGreaterZero_A	1060	1060	0	0
GntImpliesReady_A	426441338	99412633	0	0
GntImpliesValid_A	426441338	99412633	0	0
GrantKnown_A	426441338	425634549	0	0
IdxKnown_A	426441338	425634549	0	0
IndexIsCorrect_A	426441338	99412633	0	0
NoReadyValidNoGrant_A	426441338	42764819	0	0
Priority_A	426441338	105446209	0	0
ReadyAndValidImplyGrant_A	426441338	99412633	0	0
ReqAndReadyImplyGrant_A	426441338	99412633	0	0
ReqImpliesValid_A	426441338	105446209	0	0
ValidKnown_A	426441338	425634549	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	425634549	0	0
T1	2135	2085	0	0
T2	884764	884617	0	0
T3	1173	1120	0	0
T4	97119	96948	0	0
T5	78763	78672	0	0
T6	209902	209823	0	0
T7	818583	818454	0	0
T12	242765	242764	0	0
T20	1518	1430	0	0
T21	251417	251366	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	99412633	0	0
T2	884764	16120	0	0
T3	1173	0	0	0
T4	97119	14783	0	0
T5	78763	0	0	0
T6	209902	20643	0	0
T7	818583	14914	0	0
T8	42262	0	0	0
T12	242765	413257	0	0
T20	1518	17	0	0
T21	251417	110709	0	0
T22	0	845	0	0
T25	0	13	0	0
T34	0	5731	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	99412633	0	0
T2	884764	16120	0	0
T3	1173	0	0	0
T4	97119	14783	0	0
T5	78763	0	0	0
T6	209902	20643	0	0
T7	818583	14914	0	0
T8	42262	0	0	0
T12	242765	413257	0	0
T20	1518	17	0	0
T21	251417	110709	0	0
T22	0	845	0	0
T25	0	13	0	0
T34	0	5731	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	425634549	0	0
T1	2135	2085	0	0
T2	884764	884617	0	0
T3	1173	1120	0	0
T4	97119	96948	0	0
T5	78763	78672	0	0
T6	209902	209823	0	0
T7	818583	818454	0	0
T12	242765	242764	0	0
T20	1518	1430	0	0
T21	251417	251366	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	425634549	0	0
T1	2135	2085	0	0
T2	884764	884617	0	0
T3	1173	1120	0	0
T4	97119	96948	0	0
T5	78763	78672	0	0
T6	209902	209823	0	0
T7	818583	818454	0	0
T12	242765	242764	0	0
T20	1518	1430	0	0
T21	251417	251366	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	99412633	0	0
T2	884764	16120	0	0
T3	1173	0	0	0
T4	97119	14783	0	0
T5	78763	0	0	0
T6	209902	20643	0	0
T7	818583	14914	0	0
T8	42262	0	0	0
T12	242765	413257	0	0
T20	1518	17	0	0
T21	251417	110709	0	0
T22	0	845	0	0
T25	0	13	0	0
T34	0	5731	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	42764819	0	0
T2	884764	519988	0	0
T3	1173	0	0	0
T4	97119	21539	0	0
T5	78763	0	0	0
T6	209902	1686	0	0
T7	818583	486089	0	0
T8	42262	0	0	0
T12	242765	524325	0	0
T20	1518	26	0	0
T21	251417	0	0	0
T22	0	128	0	0
T25	0	20	0	0
T26	0	44449	0	0
T34	0	789	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	105446209	0	0
T2	884764	165419	0	0
T3	1173	0	0	0
T4	97119	17577	0	0
T5	78763	0	0	0
T6	209902	20643	0	0
T7	818583	133016	0	0
T8	42262	0	0	0
T12	242765	413257	0	0
T20	1518	17	0	0
T21	251417	110709	0	0
T22	0	845	0	0
T25	0	13	0	0
T34	0	5731	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	99412633	0	0
T2	884764	16120	0	0
T3	1173	0	0	0
T4	97119	14783	0	0
T5	78763	0	0	0
T6	209902	20643	0	0
T7	818583	14914	0	0
T8	42262	0	0	0
T12	242765	413257	0	0
T20	1518	17	0	0
T21	251417	110709	0	0
T22	0	845	0	0
T25	0	13	0	0
T34	0	5731	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	99412633	0	0
T2	884764	16120	0	0
T3	1173	0	0	0
T4	97119	14783	0	0
T5	78763	0	0	0
T6	209902	20643	0	0
T7	818583	14914	0	0
T8	42262	0	0	0
T12	242765	413257	0	0
T20	1518	17	0	0
T21	251417	110709	0	0
T22	0	845	0	0
T25	0	13	0	0
T34	0	5731	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	105446209	0	0
T2	884764	165419	0	0
T3	1173	0	0	0
T4	97119	17577	0	0
T5	78763	0	0	0
T6	209902	20643	0	0
T7	818583	133016	0	0
T8	42262	0	0	0
T12	242765	413257	0	0
T20	1518	17	0	0
T21	251417	110709	0	0
T22	0	845	0	0
T25	0	13	0	0
T34	0	5731	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426441338	425634549	0	0
T1	2135	2085	0	0
T2	884764	884617	0	0
T3	1173	1120	0	0
T4	97119	96948	0	0
T5	78763	78672	0	0
T6	209902	209823	0	0
T7	818583	818454	0	0
T12	242765	242764	0	0
T20	1518	1430	0	0
T21	251417	251366	0	0