Unified Coverage Report :: Module Instance :: tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	428952925	34335268	0	0
DepthKnown_A	428952925	428063621	0	0
RvalidKnown_A	428952925	428063621	0	0
WreadyKnown_A	428952925	428063621	0	0
gen_passthru_fifo.paramCheckPass	1275	1275	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428952925	34335268	0	0
T15	1016	57	0	0
T44	3164	387	0	0
T45	3484	2083	0	0
T46	3347	376	0	0
T47	2103	1391	0	0
T48	3143	400	0	0
T51	1131	57	0	0
T52	961	124	0	0
T53	1522	124	0	0
T54	1535	124	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428952925	428063621	0	0
T15	1016	922	0	0
T44	3164	3104	0	0
T45	3484	3393	0	0
T46	3347	3285	0	0
T47	2103	2042	0	0
T48	3143	3087	0	0
T51	1131	1063	0	0
T52	961	900	0	0
T53	1522	1441	0	0
T54	1535	1450	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428952925	428063621	0	0
T15	1016	922	0	0
T44	3164	3104	0	0
T45	3484	3393	0	0
T46	3347	3285	0	0
T47	2103	2042	0	0
T48	3143	3087	0	0
T51	1131	1063	0	0
T52	961	900	0	0
T53	1522	1441	0	0
T54	1535	1450	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428952925	428063621	0	0
T15	1016	922	0	0
T44	3164	3104	0	0
T45	3484	3393	0	0
T46	3347	3285	0	0
T47	2103	2042	0	0
T48	3143	3087	0	0
T51	1131	1063	0	0
T52	961	900	0	0
T53	1522	1441	0	0
T54	1535	1450	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1275	1275	0	0
T15	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T48	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	428952925	42574537	0	0
DepthKnown_A	428952925	428063621	0	0
RvalidKnown_A	428952925	428063621	0	0
WreadyKnown_A	428952925	428063621	0	0
gen_passthru_fifo.paramCheckPass	1275	1275	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428952925	42574537	0	0
T15	1016	57	0	0
T44	3164	357	0	0
T45	3484	1099	0	0
T46	3347	354	0	0
T47	2103	726	0	0
T48	3143	371	0	0
T51	1131	57	0	0
T52	961	124	0	0
T53	1522	124	0	0
T54	1535	124	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428952925	428063621	0	0
T15	1016	922	0	0
T44	3164	3104	0	0
T45	3484	3393	0	0
T46	3347	3285	0	0
T47	2103	2042	0	0
T48	3143	3087	0	0
T51	1131	1063	0	0
T52	961	900	0	0
T53	1522	1441	0	0
T54	1535	1450	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428952925	428063621	0	0
T15	1016	922	0	0
T44	3164	3104	0	0
T45	3484	3393	0	0
T46	3347	3285	0	0
T47	2103	2042	0	0
T48	3143	3087	0	0
T51	1131	1063	0	0
T52	961	900	0	0
T53	1522	1441	0	0
T54	1535	1450	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428952925	428063621	0	0
T15	1016	922	0	0
T44	3164	3104	0	0
T45	3484	3393	0	0
T46	3347	3285	0	0
T47	2103	2042	0	0
T48	3143	3087	0	0
T51	1131	1063	0	0
T52	961	900	0	0
T53	1522	1441	0	0
T54	1535	1450	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1275	1275	0	0
T15	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T48	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	428952925	3541342	0	0
DepthKnown_A	428952925	428063621	0	0
RvalidKnown_A	428952925	428063621	0	0
WreadyKnown_A	428952925	428063621	0	0
gen_passthru_fifo.paramCheckPass	1275	1275	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428952925	3541342	0	0
T45	3484	153	0	0
T46	3347	0	0	0
T47	2103	0	0	0
T48	3143	0	0	0
T49	17962	0	0	0
T51	1131	0	0	0
T52	961	0	0	0
T53	1522	0	0	0
T54	1535	0	0	0
T116	0	15	0	0
T117	0	109	0	0
T118	0	81	0	0
T119	0	17	0	0
T120	0	193	0	0
T121	0	83	0	0
T122	0	135	0	0
T123	0	167	0	0
T124	0	181	0	0
T125	1440	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428952925	428063621	0	0
T15	1016	922	0	0
T44	3164	3104	0	0
T45	3484	3393	0	0
T46	3347	3285	0	0
T47	2103	2042	0	0
T48	3143	3087	0	0
T51	1131	1063	0	0
T52	961	900	0	0
T53	1522	1441	0	0
T54	1535	1450	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428952925	428063621	0	0
T15	1016	922	0	0
T44	3164	3104	0	0
T45	3484	3393	0	0
T46	3347	3285	0	0
T47	2103	2042	0	0
T48	3143	3087	0	0
T51	1131	1063	0	0
T52	961	900	0	0
T53	1522	1441	0	0
T54	1535	1450	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428952925	428063621	0	0
T15	1016	922	0	0
T44	3164	3104	0	0
T45	3484	3393	0	0
T46	3347	3285	0	0
T47	2103	2042	0	0
T48	3143	3087	0	0
T51	1131	1063	0	0
T52	961	900	0	0
T53	1522	1441	0	0
T54	1535	1450	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1275	1275	0	0
T15	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T48	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	428952925	3689989	0	0
DepthKnown_A	428952925	428063621	0	0
RvalidKnown_A	428952925	428063621	0	0
WreadyKnown_A	428952925	428063621	0	0
gen_passthru_fifo.paramCheckPass	1275	1275	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428952925	3689989	0	0
T45	3484	141	0	0
T46	3347	0	0	0
T47	2103	0	0	0
T48	3143	0	0	0
T49	17962	0	0	0
T51	1131	0	0	0
T52	961	0	0	0
T53	1522	0	0	0
T54	1535	0	0	0
T116	0	15	0	0
T117	0	55	0	0
T118	0	72	0	0
T119	0	17	0	0
T120	0	97	0	0
T121	0	78	0	0
T122	0	110	0	0
T123	0	403	0	0
T124	0	91	0	0
T125	1440	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428952925	428063621	0	0
T15	1016	922	0	0
T44	3164	3104	0	0
T45	3484	3393	0	0
T46	3347	3285	0	0
T47	2103	2042	0	0
T48	3143	3087	0	0
T51	1131	1063	0	0
T52	961	900	0	0
T53	1522	1441	0	0
T54	1535	1450	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428952925	428063621	0	0
T15	1016	922	0	0
T44	3164	3104	0	0
T45	3484	3393	0	0
T46	3347	3285	0	0
T47	2103	2042	0	0
T48	3143	3087	0	0
T51	1131	1063	0	0
T52	961	900	0	0
T53	1522	1441	0	0
T54	1535	1450	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428952925	428063621	0	0
T15	1016	922	0	0
T44	3164	3104	0	0
T45	3484	3393	0	0
T46	3347	3285	0	0
T47	2103	2042	0	0
T48	3143	3087	0	0
T51	1131	1063	0	0
T52	961	900	0	0
T53	1522	1441	0	0
T54	1535	1450	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1275	1275	0	0
T15	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T48	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0