SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[flash_ctrl_core_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[flash_ctrl_eflash_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[flash_ctrl_prim_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 23314731 | 1 | T16 | 103 | T48 | 7925 | T49 | 965 | |||
auto[1] | 4542448 | 1 | T48 | 7 | T49 | 162 | T53 | 277 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 27856995 | 1 | T16 | 103 | T48 | 7919 | T49 | 1127 | |||
values[1] | 13 | 1 | T48 | 1 | T249 | 2 | T289 | 3 | |||
values[2] | 4 | 1 | T251 | 1 | T270 | 1 | T342 | 1 | |||
values[3] | 94 | 1 | T48 | 7 | T195 | 5 | T248 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 27856986 | 1 | T16 | 103 | T48 | 7921 | T49 | 1127 | |||
values[1] | 15 | 1 | T48 | 2 | T195 | 1 | T248 | 1 | |||
values[2] | 5 | 1 | T250 | 1 | T289 | 1 | T285 | 1 | |||
values[3] | 102 | 1 | T48 | 4 | T195 | 3 | T248 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 27856889 | 1 | T16 | 103 | T48 | 7912 | T49 | 1127 | |||
auto[TlIntgErrCmd] | 97 | 1 | T48 | 9 | T195 | 4 | T248 | 3 | |||
auto[TlIntgErrData] | 106 | 1 | T48 | 7 | T195 | 4 | T248 | 3 | |||
auto[TlIntgErrBoth] | 87 | 1 | T48 | 4 | T195 | 2 | T248 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[0]] | 0 | 0 | - | - | - | - | - | - | |||
auto[1] | 4101518 | 0 | T48 | 20 | T49 | 1433 | T53 | 941 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 4101348 | 1 | T48 | 11 | T49 | 1433 | T53 | 941 | |||
values[1] | 13 | 1 | T195 | 1 | T270 | 1 | T284 | 2 | |||
values[2] | 4 | 1 | T248 | 1 | T249 | 1 | T251 | 1 | |||
values[3] | 88 | 1 | T48 | 3 | T248 | 3 | T250 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 4101323 | 1 | T48 | 7 | T49 | 1433 | T53 | 941 | |||
values[1] | 14 | 1 | T48 | 2 | T195 | 1 | T250 | 1 | |||
values[2] | 5 | 1 | T195 | 1 | T251 | 1 | T289 | 1 | |||
values[3] | 104 | 1 | T48 | 6 | T195 | 3 | T248 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 4101243 | 1 | T49 | 1433 | T53 | 941 | T54 | 974 | |||
auto[TlIntgErrCmd] | 80 | 1 | T48 | 7 | T195 | 3 | T248 | 2 | |||
auto[TlIntgErrData] | 105 | 1 | T48 | 11 | T195 | 6 | T248 | 5 | |||
auto[TlIntgErrBoth] | 90 | 1 | T48 | 2 | T195 | 1 | T248 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 75723 | 0 | T48 | 1301 | T49 | 772 | T53 | 390 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 75544 | 1 | T48 | 1288 | T49 | 772 | T53 | 390 | |||
values[1] | 16 | 1 | T48 | 2 | T195 | 1 | T248 | 1 | |||
values[2] | 6 | 1 | T248 | 1 | T250 | 1 | T251 | 1 | |||
values[3] | 98 | 1 | T48 | 10 | T195 | 4 | T248 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 75515 | 1 | T48 | 1287 | T49 | 772 | T53 | 390 | |||
values[1] | 34 | 1 | T48 | 2 | T195 | 1 | T250 | 2 | |||
values[2] | 5 | 1 | T48 | 1 | T195 | 1 | T270 | 1 | |||
values[3] | 100 | 1 | T48 | 4 | T195 | 2 | T248 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 75433 | 1 | T48 | 1281 | T49 | 772 | T53 | 390 | |||
auto[TlIntgErrCmd] | 82 | 1 | T48 | 6 | T195 | 2 | T248 | 1 | |||
auto[TlIntgErrData] | 111 | 1 | T48 | 7 | T195 | 4 | T248 | 4 | |||
auto[TlIntgErrBoth] | 97 | 1 | T48 | 7 | T195 | 4 | T248 | 5 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |