Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	21047541	1		T16	64		T48	6117		T49	602
full_word	6809638	1		T16	39		T48	1815		T49	525

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	27856889	1		T16	103		T48	7912		T49	1127
auto[TlIntgErrCmd]	97	1		T48	9		T195	4		T248	3
auto[TlIntgErrData]	106	1		T48	7		T195	4		T248	3
auto[TlIntgErrBoth]	87	1		T48	4		T195	2		T248	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	24015347	1		T16	58		T48	5861		T49	721
auto[1]	3841832	1		T16	45		T48	2071		T49	406

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	20465844	1		T16	58		T48	5358		T49	545
auto[TlIntgErrNone]	partial	auto[1]	581422	1		T16	6		T48	740		T49	57
auto[TlIntgErrNone]	full_word	auto[0]	3549368	1		T48	494		T49	176		T51	1
auto[TlIntgErrNone]	full_word	auto[1]	3260255	1		T16	39		T48	1320		T49	349
auto[TlIntgErrCmd]	partial	auto[0]	36	1		T48	2		T248	2		T250	2
auto[TlIntgErrCmd]	partial	auto[1]	57	1		T48	6		T195	4		T248	1
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T251	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T48	1		T343	1		T285	1
auto[TlIntgErrData]	partial	auto[0]	52	1		T48	4		T195	2		T250	3
auto[TlIntgErrData]	partial	auto[1]	46	1		T48	3		T195	2		T248	2
auto[TlIntgErrData]	full_word	auto[0]	5	1		T248	1		T250	1		T284	1
auto[TlIntgErrData]	full_word	auto[1]	3	1		T251	1		T284	1		T344	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1		T48	3		T195	1		T248	3
auto[TlIntgErrBoth]	partial	auto[1]	44	1		T48	1		T195	1		T248	1
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T344	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1		T345	2		-	-		-	-

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	23491	1		T48	18		T49	1063		T53	586
full_word	4078027	1		T48	2		T49	370		T53	355

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4101243	1		T49	1433		T53	941		T54	974
auto[TlIntgErrCmd]	80	1		T48	7		T195	3		T248	2
auto[TlIntgErrData]	105	1		T48	11		T195	6		T248	5
auto[TlIntgErrBoth]	90	1		T48	2		T195	1		T248	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4072890	1		T48	12		T49	100		T53	63
auto[1]	28628	1		T48	8		T49	1333		T53	878

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1368	1		T49	86		T53	57		T54	23
auto[TlIntgErrNone]	partial	auto[1]	21869	1		T49	977		T53	529		T54	747
auto[TlIntgErrNone]	full_word	auto[0]	4071401	1		T49	14		T53	6		T54	8
auto[TlIntgErrNone]	full_word	auto[1]	6605	1		T49	356		T53	349		T54	196
auto[TlIntgErrCmd]	partial	auto[0]	29	1		T48	2		T195	2		T250	1
auto[TlIntgErrCmd]	partial	auto[1]	47	1		T48	4		T195	1		T248	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T249	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T48	1		T289	1		T346	1
auto[TlIntgErrData]	partial	auto[0]	54	1		T48	9		T195	5		T248	2
auto[TlIntgErrData]	partial	auto[1]	41	1		T48	2		T195	1		T248	2
auto[TlIntgErrData]	full_word	auto[0]	5	1		T343	1		T270	1		T285	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T248	1		T323	1		T285	1
auto[TlIntgErrBoth]	partial	auto[0]	30	1		T248	1		T250	2		T249	1
auto[TlIntgErrBoth]	partial	auto[1]	53	1		T48	1		T195	1		T248	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T48	1		T345	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T289	2		T347	1		T348	2