Group : dv_base_reg_pkg::mubi_cov#(4,32'sb00000000000000000000000000000101,32'sb00000000000000000000000000001010)::mubi_cg
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Group Instance : mubi4_cov_of_tb.dut.u_lc_escalate_en_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
83.33 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_tb.dut.u_lc_escalate_en_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 1 5 83.33


Variables for Group Instance mubi4_cov_of_tb.dut.u_lc_escalate_en_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 1 5 83.33 100 1 1 0



Group Instance : mubi4_cov_of_tb.dut.u_lc_creator_seed_sw_rw_en_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_tb.dut.u_lc_creator_seed_sw_rw_en_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_tb.dut.u_lc_creator_seed_sw_rw_en_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_tb.dut.u_lc_iso_part_sw_rd_en_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_tb.dut.u_lc_iso_part_sw_rd_en_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_tb.dut.u_lc_iso_part_sw_rd_en_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_tb.dut.u_lc_iso_part_sw_wr_en_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_tb.dut.u_lc_iso_part_sw_wr_en_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_tb.dut.u_lc_iso_part_sw_wr_en_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_tb.dut.u_lc_nvm_debug_en_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_tb.dut.u_lc_nvm_debug_en_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_tb.dut.u_lc_nvm_debug_en_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_tb.dut.u_lc_owner_seed_sw_rw_en_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_tb.dut.u_lc_owner_seed_sw_rw_en_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_tb.dut.u_lc_owner_seed_sw_rw_en_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_tb.dut.u_lc_seed_hw_rd_en_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_tb.dut.u_lc_seed_hw_rd_en_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_tb.dut.u_lc_seed_hw_rd_en_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 1 5 83.33


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBER
others[2] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 5 1 T174 1 T176 1 T349 1
others[1] 7 1 T28 1 T350 1 T351 1
others[3] 8 1 T6 1 T175 1 T352 1
false 11283 1 T16 1 T48 61 T49 3
true 4 1 T80 1 T353 1 T354 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 80 1 T4 3 T25 2 T81 2
others[1] 91 1 T4 2 T25 2 T62 2
others[2] 78 1 T4 1 T25 1 T62 3
others[3] 124 1 T4 2 T25 3 T62 2
false 24874 1 T48 61 T49 3 T51 1
true 20135 1 T16 2 T53 2 T54 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 2089 1 T25 1 T23 51 T81 1
others[1] 2112 1 T4 1 T25 1 T23 45
others[2] 2091 1 T2 2 T23 54 T62 3
others[3] 3548 1 T4 3 T84 2 T23 90
false 6837 1 T48 61 T49 3 T51 1
true 1526 1 T16 2 T53 1 T54 2


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 2147 1 T4 1 T25 1 T23 61
others[1] 2095 1 T23 34 T192 87 T193 56
others[2] 2103 1 T25 3 T23 63 T192 85
others[3] 3497 1 T2 2 T4 2 T84 2
false 6809 1 T48 61 T49 3 T51 1
true 1523 1 T16 2 T53 1 T54 2


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 2085 1 T23 68 T192 101 T193 61
others[1] 2132 1 T200 1 T23 40 T355 1
others[2] 2109 1 T84 2 T23 52 T192 75
others[3] 3549 1 T23 88 T192 159 T246 1
false 7147 1 T16 1 T48 61 T49 3
true 39 1 T20 1 T21 1 T194 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 86 1 T4 1 T25 2 T62 2
others[1] 96 1 T4 4 T25 3 T62 2
others[2] 79 1 T4 1 T25 2 T81 2
others[3] 123 1 T4 1 T25 3 T62 4
false 24944 1 T16 1 T48 61 T49 3
true 20297 1 T16 1 T53 1 T54 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 6758 1 T23 151 T192 265 T193 162
others[1] 6942 1 T23 178 T192 290 T193 169
others[2] 6715 1 T23 170 T192 269 T164 3
others[3] 11447 1 T23 306 T192 486 T193 290
false 3457 1 T23 79 T192 144 T193 77
true 17489 1 T16 1 T48 61 T49 3

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