Line Coverage for Module :
flash_phy_rd_buf_dep
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 48 | 7 | 7 | 100.00 |
CONT_ASSIGN | 61 | 1 | 1 | 100.00 |
CONT_ASSIGN | 62 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 66 | 1 | 1 | 100.00 |
CONT_ASSIGN | 71 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
ALWAYS | 76 | 6 | 6 | 100.00 |
ALWAYS | 90 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
ALWAYS | 116 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
|
|
|
MISSING_ELSE |
54 |
1 |
1 |
55 |
1 |
1 |
|
|
|
MISSING_ELSE |
61 |
1 |
1 |
62 |
1 |
1 |
65 |
1 |
1 |
66 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
76 |
1 |
1 |
77 |
1 |
1 |
79 |
1 |
1 |
80 |
1 |
1 |
|
|
|
MISSING_ELSE |
82 |
1 |
1 |
83 |
1 |
1 |
|
|
|
MISSING_ELSE |
90 |
1 |
1 |
91 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
116 |
|
unreachable |
117 |
|
unreachable |
118 |
|
unreachable |
Cond Coverage for Module :
flash_phy_rd_buf_dep
| Total | Covered | Percent |
Conditions | 22 | 19 | 86.36 |
Logical | 22 | 19 | 86.36 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
--1- ----2---- -----------------------3----------------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T4,T6 |
LINE 66
EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
--1- ----2---- ----------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T4,T6 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T4,T6 |
LINE 71
EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T4,T6 |
1 | Covered | T1,T2,T3 |
LINE 71
SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 71
SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
----1--- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T10,T8 |
1 | 1 | Covered | T1,T4,T6 |
LINE 72
EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T4,T6 |
1 | Covered | T1,T2,T3 |
LINE 72
SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 72
SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
------1------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T10,T8 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T6 |
Branch Coverage for Module :
flash_phy_rd_buf_dep
| Line No. | Total | Covered | Percent |
Branches |
|
13 |
13 |
100.00 |
TERNARY |
71 |
2 |
2 |
100.00 |
TERNARY |
72 |
2 |
2 |
100.00 |
IF |
51 |
2 |
2 |
100.00 |
IF |
54 |
2 |
2 |
100.00 |
IF |
76 |
5 |
5 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 ((incr_buf_sel == decr_buf_sel)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T4,T6 |
LineNo. Expression
-1-: 72 ((incr_buf_sel == decr_buf_sel)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T4,T6 |
LineNo. Expression
-1-: 51 if (wr_buf_i[i])
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T6 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 54 if (rd_buf_i[i])
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T6 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 76 if ((!rst_ni))
-2-: 79 if (fin_cnt_incr)
-3-: 82 if (fin_cnt_decr)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T4,T6 |
0 |
0 |
- |
Covered |
T1,T2,T3 |
0 |
- |
1 |
Covered |
T1,T4,T6 |
0 |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
flash_phy_rd_buf_dep
Assertion Details
BufferDecrUnderRun_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
825123306 |
6520967 |
0 |
0 |
T1 |
670774 |
47727 |
0 |
0 |
T2 |
800868 |
0 |
0 |
0 |
T3 |
6786 |
0 |
0 |
0 |
T4 |
97076 |
512 |
0 |
0 |
T5 |
145828 |
1489 |
0 |
0 |
T6 |
2106 |
14 |
0 |
0 |
T7 |
0 |
52 |
0 |
0 |
T8 |
90876 |
21815 |
0 |
0 |
T9 |
0 |
322 |
0 |
0 |
T10 |
28464 |
251 |
0 |
0 |
T20 |
2200 |
0 |
0 |
0 |
T21 |
1888 |
0 |
0 |
0 |
T23 |
0 |
3752 |
0 |
0 |
T24 |
0 |
33731 |
0 |
0 |
T44 |
0 |
32144 |
0 |
0 |
T45 |
0 |
23355 |
0 |
0 |
T46 |
0 |
23577 |
0 |
0 |
T47 |
0 |
22651 |
0 |
0 |
BufferDepRsp_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
825123306 |
823601392 |
0 |
0 |
T1 |
670774 |
670576 |
0 |
0 |
T2 |
800868 |
800836 |
0 |
0 |
T3 |
6786 |
5600 |
0 |
0 |
T4 |
97076 |
96940 |
0 |
0 |
T5 |
145828 |
145630 |
0 |
0 |
T6 |
2106 |
1972 |
0 |
0 |
T8 |
90876 |
90750 |
0 |
0 |
T10 |
28464 |
28250 |
0 |
0 |
T20 |
2200 |
2034 |
0 |
0 |
T21 |
1888 |
1788 |
0 |
0 |
BufferIncrOverFlow_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
825123306 |
6520987 |
0 |
0 |
T1 |
670774 |
47727 |
0 |
0 |
T2 |
800868 |
0 |
0 |
0 |
T3 |
6786 |
0 |
0 |
0 |
T4 |
97076 |
512 |
0 |
0 |
T5 |
145828 |
1489 |
0 |
0 |
T6 |
2106 |
14 |
0 |
0 |
T7 |
0 |
52 |
0 |
0 |
T8 |
90876 |
21815 |
0 |
0 |
T9 |
0 |
322 |
0 |
0 |
T10 |
28464 |
251 |
0 |
0 |
T20 |
2200 |
0 |
0 |
0 |
T21 |
1888 |
0 |
0 |
0 |
T23 |
0 |
3752 |
0 |
0 |
T24 |
0 |
33731 |
0 |
0 |
T44 |
0 |
32144 |
0 |
0 |
T45 |
0 |
23355 |
0 |
0 |
T46 |
0 |
23577 |
0 |
0 |
T47 |
0 |
22651 |
0 |
0 |
DepBufferRspOrder_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
825123309 |
16465661 |
0 |
0 |
T1 |
670774 |
47759 |
0 |
0 |
T2 |
800868 |
263744 |
0 |
0 |
T3 |
6786 |
166 |
0 |
0 |
T4 |
97076 |
544 |
0 |
0 |
T5 |
145828 |
1521 |
0 |
0 |
T6 |
2106 |
46 |
0 |
0 |
T8 |
90876 |
21847 |
0 |
0 |
T9 |
0 |
142 |
0 |
0 |
T10 |
28464 |
315 |
0 |
0 |
T20 |
2200 |
32 |
0 |
0 |
T21 |
1888 |
32 |
0 |
0 |
T24 |
0 |
14142 |
0 |
0 |
T44 |
0 |
15837 |
0 |
0 |
T45 |
0 |
23355 |
0 |
0 |
T84 |
0 |
131072 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 48 | 7 | 7 | 100.00 |
CONT_ASSIGN | 61 | 1 | 1 | 100.00 |
CONT_ASSIGN | 62 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 66 | 1 | 1 | 100.00 |
CONT_ASSIGN | 71 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
ALWAYS | 76 | 6 | 6 | 100.00 |
ALWAYS | 90 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
ALWAYS | 116 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
|
|
|
MISSING_ELSE |
54 |
1 |
1 |
55 |
1 |
1 |
|
|
|
MISSING_ELSE |
61 |
1 |
1 |
62 |
1 |
1 |
65 |
1 |
1 |
66 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
76 |
1 |
1 |
77 |
1 |
1 |
79 |
1 |
1 |
80 |
1 |
1 |
|
|
|
MISSING_ELSE |
82 |
1 |
1 |
83 |
1 |
1 |
|
|
|
MISSING_ELSE |
90 |
1 |
1 |
91 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
116 |
|
unreachable |
117 |
|
unreachable |
118 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
| Total | Covered | Percent |
Conditions | 22 | 19 | 86.36 |
Logical | 22 | 19 | 86.36 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
--1- ----2---- -----------------------3----------------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T4,T6 |
LINE 66
EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
--1- ----2---- ----------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T4,T6 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T4,T6 |
LINE 71
EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T4,T6 |
1 | Covered | T1,T2,T3 |
LINE 71
SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 71
SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
----1--- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T7,T9 |
1 | 1 | Covered | T1,T4,T6 |
LINE 72
EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T4,T6 |
1 | Covered | T1,T2,T3 |
LINE 72
SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 72
SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
------1------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T7,T9 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T6 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
| Line No. | Total | Covered | Percent |
Branches |
|
13 |
13 |
100.00 |
TERNARY |
71 |
2 |
2 |
100.00 |
TERNARY |
72 |
2 |
2 |
100.00 |
IF |
51 |
2 |
2 |
100.00 |
IF |
54 |
2 |
2 |
100.00 |
IF |
76 |
5 |
5 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 ((incr_buf_sel == decr_buf_sel)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T4,T6 |
LineNo. Expression
-1-: 72 ((incr_buf_sel == decr_buf_sel)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T4,T6 |
LineNo. Expression
-1-: 51 if (wr_buf_i[i])
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T6 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 54 if (rd_buf_i[i])
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T6 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 76 if ((!rst_ni))
-2-: 79 if (fin_cnt_incr)
-3-: 82 if (fin_cnt_decr)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T4,T6 |
0 |
0 |
- |
Covered |
T1,T2,T3 |
0 |
- |
1 |
Covered |
T1,T4,T6 |
0 |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
Assertion Details
BufferDecrUnderRun_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412561653 |
3446438 |
0 |
0 |
T1 |
335387 |
23868 |
0 |
0 |
T2 |
400434 |
0 |
0 |
0 |
T3 |
3393 |
0 |
0 |
0 |
T4 |
48538 |
512 |
0 |
0 |
T5 |
72914 |
771 |
0 |
0 |
T6 |
1053 |
14 |
0 |
0 |
T7 |
0 |
52 |
0 |
0 |
T8 |
45438 |
9609 |
0 |
0 |
T9 |
0 |
180 |
0 |
0 |
T10 |
14232 |
0 |
0 |
0 |
T20 |
1100 |
0 |
0 |
0 |
T21 |
944 |
0 |
0 |
0 |
T23 |
0 |
3752 |
0 |
0 |
T24 |
0 |
19589 |
0 |
0 |
T44 |
0 |
16307 |
0 |
0 |
BufferDepRsp_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412561653 |
411800696 |
0 |
0 |
T1 |
335387 |
335288 |
0 |
0 |
T2 |
400434 |
400418 |
0 |
0 |
T3 |
3393 |
2800 |
0 |
0 |
T4 |
48538 |
48470 |
0 |
0 |
T5 |
72914 |
72815 |
0 |
0 |
T6 |
1053 |
986 |
0 |
0 |
T8 |
45438 |
45375 |
0 |
0 |
T10 |
14232 |
14125 |
0 |
0 |
T20 |
1100 |
1017 |
0 |
0 |
T21 |
944 |
894 |
0 |
0 |
BufferIncrOverFlow_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412561653 |
3446451 |
0 |
0 |
T1 |
335387 |
23868 |
0 |
0 |
T2 |
400434 |
0 |
0 |
0 |
T3 |
3393 |
0 |
0 |
0 |
T4 |
48538 |
512 |
0 |
0 |
T5 |
72914 |
771 |
0 |
0 |
T6 |
1053 |
14 |
0 |
0 |
T7 |
0 |
52 |
0 |
0 |
T8 |
45438 |
9609 |
0 |
0 |
T9 |
0 |
180 |
0 |
0 |
T10 |
14232 |
0 |
0 |
0 |
T20 |
1100 |
0 |
0 |
0 |
T21 |
944 |
0 |
0 |
0 |
T23 |
0 |
3752 |
0 |
0 |
T24 |
0 |
19589 |
0 |
0 |
T44 |
0 |
16307 |
0 |
0 |
DepBufferRspOrder_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412561655 |
8873954 |
0 |
0 |
T1 |
335387 |
23900 |
0 |
0 |
T2 |
400434 |
132672 |
0 |
0 |
T3 |
3393 |
166 |
0 |
0 |
T4 |
48538 |
544 |
0 |
0 |
T5 |
72914 |
803 |
0 |
0 |
T6 |
1053 |
46 |
0 |
0 |
T8 |
45438 |
9641 |
0 |
0 |
T10 |
14232 |
64 |
0 |
0 |
T20 |
1100 |
32 |
0 |
0 |
T21 |
944 |
32 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 48 | 7 | 7 | 100.00 |
CONT_ASSIGN | 61 | 1 | 1 | 100.00 |
CONT_ASSIGN | 62 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 66 | 1 | 1 | 100.00 |
CONT_ASSIGN | 71 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
ALWAYS | 76 | 6 | 6 | 100.00 |
ALWAYS | 90 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
ALWAYS | 116 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
|
|
|
MISSING_ELSE |
54 |
1 |
1 |
55 |
1 |
1 |
|
|
|
MISSING_ELSE |
61 |
1 |
1 |
62 |
1 |
1 |
65 |
1 |
1 |
66 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
76 |
1 |
1 |
77 |
1 |
1 |
79 |
1 |
1 |
80 |
1 |
1 |
|
|
|
MISSING_ELSE |
82 |
1 |
1 |
83 |
1 |
1 |
|
|
|
MISSING_ELSE |
90 |
1 |
1 |
91 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
116 |
|
unreachable |
117 |
|
unreachable |
118 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
| Total | Covered | Percent |
Conditions | 22 | 19 | 86.36 |
Logical | 22 | 19 | 86.36 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
--1- ----2---- -----------------------3----------------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T84,T149 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T10,T5 |
LINE 66
EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
--1- ----2---- ----------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T10,T5 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T10,T5 |
LINE 71
EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T10,T5 |
1 | Covered | T1,T2,T3 |
LINE 71
SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 71
SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
----1--- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T10,T8,T9 |
1 | 1 | Covered | T1,T10,T5 |
LINE 72
EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T10,T5 |
1 | Covered | T1,T2,T3 |
LINE 72
SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 72
SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
------1------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T10,T8,T9 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T10,T5 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
| Line No. | Total | Covered | Percent |
Branches |
|
13 |
13 |
100.00 |
TERNARY |
71 |
2 |
2 |
100.00 |
TERNARY |
72 |
2 |
2 |
100.00 |
IF |
51 |
2 |
2 |
100.00 |
IF |
54 |
2 |
2 |
100.00 |
IF |
76 |
5 |
5 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 ((incr_buf_sel == decr_buf_sel)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T10,T5 |
LineNo. Expression
-1-: 72 ((incr_buf_sel == decr_buf_sel)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T10,T5 |
LineNo. Expression
-1-: 51 if (wr_buf_i[i])
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T10,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 54 if (rd_buf_i[i])
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T10,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 76 if ((!rst_ni))
-2-: 79 if (fin_cnt_incr)
-3-: 82 if (fin_cnt_decr)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T10,T5 |
0 |
0 |
- |
Covered |
T1,T2,T3 |
0 |
- |
1 |
Covered |
T1,T10,T5 |
0 |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
Assertion Details
BufferDecrUnderRun_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412561653 |
3074529 |
0 |
0 |
T1 |
335387 |
23859 |
0 |
0 |
T2 |
400434 |
0 |
0 |
0 |
T3 |
3393 |
0 |
0 |
0 |
T4 |
48538 |
0 |
0 |
0 |
T5 |
72914 |
718 |
0 |
0 |
T6 |
1053 |
0 |
0 |
0 |
T8 |
45438 |
12206 |
0 |
0 |
T9 |
0 |
142 |
0 |
0 |
T10 |
14232 |
251 |
0 |
0 |
T20 |
1100 |
0 |
0 |
0 |
T21 |
944 |
0 |
0 |
0 |
T24 |
0 |
14142 |
0 |
0 |
T44 |
0 |
15837 |
0 |
0 |
T45 |
0 |
23355 |
0 |
0 |
T46 |
0 |
23577 |
0 |
0 |
T47 |
0 |
22651 |
0 |
0 |
BufferDepRsp_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412561653 |
411800696 |
0 |
0 |
T1 |
335387 |
335288 |
0 |
0 |
T2 |
400434 |
400418 |
0 |
0 |
T3 |
3393 |
2800 |
0 |
0 |
T4 |
48538 |
48470 |
0 |
0 |
T5 |
72914 |
72815 |
0 |
0 |
T6 |
1053 |
986 |
0 |
0 |
T8 |
45438 |
45375 |
0 |
0 |
T10 |
14232 |
14125 |
0 |
0 |
T20 |
1100 |
1017 |
0 |
0 |
T21 |
944 |
894 |
0 |
0 |
BufferIncrOverFlow_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412561653 |
3074536 |
0 |
0 |
T1 |
335387 |
23859 |
0 |
0 |
T2 |
400434 |
0 |
0 |
0 |
T3 |
3393 |
0 |
0 |
0 |
T4 |
48538 |
0 |
0 |
0 |
T5 |
72914 |
718 |
0 |
0 |
T6 |
1053 |
0 |
0 |
0 |
T8 |
45438 |
12206 |
0 |
0 |
T9 |
0 |
142 |
0 |
0 |
T10 |
14232 |
251 |
0 |
0 |
T20 |
1100 |
0 |
0 |
0 |
T21 |
944 |
0 |
0 |
0 |
T24 |
0 |
14142 |
0 |
0 |
T44 |
0 |
15837 |
0 |
0 |
T45 |
0 |
23355 |
0 |
0 |
T46 |
0 |
23577 |
0 |
0 |
T47 |
0 |
22651 |
0 |
0 |
DepBufferRspOrder_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412561654 |
7591707 |
0 |
0 |
T1 |
335387 |
23859 |
0 |
0 |
T2 |
400434 |
131072 |
0 |
0 |
T3 |
3393 |
0 |
0 |
0 |
T4 |
48538 |
0 |
0 |
0 |
T5 |
72914 |
718 |
0 |
0 |
T6 |
1053 |
0 |
0 |
0 |
T8 |
45438 |
12206 |
0 |
0 |
T9 |
0 |
142 |
0 |
0 |
T10 |
14232 |
251 |
0 |
0 |
T20 |
1100 |
0 |
0 |
0 |
T21 |
944 |
0 |
0 |
0 |
T24 |
0 |
14142 |
0 |
0 |
T44 |
0 |
15837 |
0 |
0 |
T45 |
0 |
23355 |
0 |
0 |
T84 |
0 |
131072 |
0 |
0 |