Line Coverage for Module :
prim_arbiter_tree
| Line No. | Total | Covered | Percent |
TOTAL | | 52 | 48 | 92.31 |
CONT_ASSIGN | 62 | 0 | 0 | |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 174 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 182 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
ALWAYS | 191 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
62 |
|
unreachable |
112 |
4 |
4 |
118 |
4 |
4 |
122 |
0 |
4 |
126 |
4 |
4 |
128 |
4 |
4 |
148 |
3 |
3 |
150 |
3 |
3 |
151 |
3 |
3 |
155 |
3 |
3 |
156 |
3 |
3 |
160 |
3 |
3 |
161 |
3 |
3 |
163 |
1 |
1(2 unreachable) |
164 |
3 |
3 |
174 |
1 |
1 |
180 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
194 |
1 |
1 |
Cond Coverage for Module :
prim_arbiter_tree
| Total | Covered | Percent |
Conditions | 130 | 127 | 97.69 |
Logical | 130 | 127 | 97.69 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 118
EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T6,T10 |
1 | 0 | Covered | T1,T4,T6 |
1 | 1 | Covered | T1,T4,T6 |
LINE 118
EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T6,T10 |
1 | 0 | Covered | T1,T4,T6 |
1 | 1 | Covered | T1,T4,T6 |
LINE 118
EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T6,T10 |
1 | 0 | Covered | T1,T4,T6 |
1 | 1 | Covered | T1,T4,T6 |
LINE 118
EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T9,T45 |
1 | 1 | Covered | T1,T4,T6 |
LINE 126
EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T4,T6 |
1 | 1 | 0 | Covered | T1,T4,T6 |
1 | 1 | 1 | Covered | T1,T4,T6 |
LINE 126
EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T4,T6 |
1 | 1 | 0 | Covered | T1,T4,T6 |
1 | 1 | 1 | Covered | T1,T4,T6 |
LINE 126
EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T4,T6 |
1 | 1 | 0 | Covered | T1,T4,T6 |
1 | 1 | 1 | Covered | T1,T4,T6 |
LINE 126
EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T4,T6 |
1 | 1 | 0 | Covered | T1,T4,T6 |
1 | 1 | 1 | Covered | T1,T4,T6 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T6 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T6 |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Unreachable | |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T4,T6 |
1 | 1 | Covered | T1,T4,T6 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T6 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T6 |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T4,T6 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T4,T6 |
1 | 1 | Covered | T1,T4,T6 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T6 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T6 |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T4,T6 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T4,T6 |
1 | 1 | Covered | T1,T4,T6 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T6 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T6 |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T4,T6 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T4,T6 |
1 | 1 | Covered | T1,T4,T6 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T6 |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T6 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T6 |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T6 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T6 |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T6 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T24,T44 |
1 | 0 | Covered | T1,T8,T24 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T4,T6 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T4,T6 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T24,T44 |
1 | 0 | Covered | T1,T4,T6 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T8,T9 |
1 | 0 | Covered | T1,T4,T6 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T4,T6 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T4,T6 |
1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T4,T6 |
1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1- | Status | Tests |
0 | Covered | T1,T4,T6 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T4,T6 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T4,T6 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1- | Status | Tests |
0 | Covered | T1,T4,T6 |
1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T6 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T4,T6 |
1 | 1 | Covered | T1,T4,T6 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T6 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T4,T6 |
1 | 1 | Covered | T1,T2,T3 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T4,T6 |
1 | 1 | Covered | T1,T4,T6 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T10,T8 |
1 | 0 | Covered | T1,T4,T6 |
1 | 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Unreachable | |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Unreachable | |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T4,T6 |
Branch Coverage for Module :
prim_arbiter_tree
| Line No. | Total | Covered | Percent |
Branches |
|
22 |
22 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
IF |
191 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T4,T6 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T4,T6 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T4,T6 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T4,T6 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T4,T6 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T4,T6 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T6 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T6 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T6 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T6 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_arbiter_tree
Assertion Details
CheckHotOne_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
825123306 |
823601392 |
0 |
0 |
T1 |
670774 |
670576 |
0 |
0 |
T2 |
800868 |
800836 |
0 |
0 |
T3 |
6786 |
5600 |
0 |
0 |
T4 |
97076 |
96940 |
0 |
0 |
T5 |
145828 |
145630 |
0 |
0 |
T6 |
2106 |
1972 |
0 |
0 |
T8 |
90876 |
90750 |
0 |
0 |
T10 |
28464 |
28250 |
0 |
0 |
T20 |
2200 |
2034 |
0 |
0 |
T21 |
1888 |
1788 |
0 |
0 |
CheckNGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2104 |
2104 |
0 |
0 |
T1 |
2 |
2 |
0 |
0 |
T2 |
2 |
2 |
0 |
0 |
T3 |
2 |
2 |
0 |
0 |
T4 |
2 |
2 |
0 |
0 |
T5 |
2 |
2 |
0 |
0 |
T6 |
2 |
2 |
0 |
0 |
T8 |
2 |
2 |
0 |
0 |
T10 |
2 |
2 |
0 |
0 |
T20 |
2 |
2 |
0 |
0 |
T21 |
2 |
2 |
0 |
0 |
GntImpliesReady_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
825123306 |
5293737 |
0 |
0 |
T1 |
670774 |
46197 |
0 |
0 |
T2 |
800868 |
0 |
0 |
0 |
T3 |
6786 |
0 |
0 |
0 |
T4 |
97076 |
252 |
0 |
0 |
T5 |
145828 |
746 |
0 |
0 |
T6 |
2106 |
4 |
0 |
0 |
T7 |
0 |
24 |
0 |
0 |
T8 |
90876 |
19695 |
0 |
0 |
T9 |
0 |
314 |
0 |
0 |
T10 |
28464 |
124 |
0 |
0 |
T20 |
2200 |
0 |
0 |
0 |
T21 |
1888 |
0 |
0 |
0 |
T23 |
0 |
684 |
0 |
0 |
T24 |
0 |
25914 |
0 |
0 |
T44 |
0 |
25176 |
0 |
0 |
T45 |
0 |
23045 |
0 |
0 |
T46 |
0 |
23047 |
0 |
0 |
T47 |
0 |
22138 |
0 |
0 |
GntImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
825123306 |
5293737 |
0 |
0 |
T1 |
670774 |
46197 |
0 |
0 |
T2 |
800868 |
0 |
0 |
0 |
T3 |
6786 |
0 |
0 |
0 |
T4 |
97076 |
252 |
0 |
0 |
T5 |
145828 |
746 |
0 |
0 |
T6 |
2106 |
4 |
0 |
0 |
T7 |
0 |
24 |
0 |
0 |
T8 |
90876 |
19695 |
0 |
0 |
T9 |
0 |
314 |
0 |
0 |
T10 |
28464 |
124 |
0 |
0 |
T20 |
2200 |
0 |
0 |
0 |
T21 |
1888 |
0 |
0 |
0 |
T23 |
0 |
684 |
0 |
0 |
T24 |
0 |
25914 |
0 |
0 |
T44 |
0 |
25176 |
0 |
0 |
T45 |
0 |
23045 |
0 |
0 |
T46 |
0 |
23047 |
0 |
0 |
T47 |
0 |
22138 |
0 |
0 |
GrantKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
825123306 |
823601392 |
0 |
0 |
T1 |
670774 |
670576 |
0 |
0 |
T2 |
800868 |
800836 |
0 |
0 |
T3 |
6786 |
5600 |
0 |
0 |
T4 |
97076 |
96940 |
0 |
0 |
T5 |
145828 |
145630 |
0 |
0 |
T6 |
2106 |
1972 |
0 |
0 |
T8 |
90876 |
90750 |
0 |
0 |
T10 |
28464 |
28250 |
0 |
0 |
T20 |
2200 |
2034 |
0 |
0 |
T21 |
1888 |
1788 |
0 |
0 |
IdxKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
825123306 |
823601392 |
0 |
0 |
T1 |
670774 |
670576 |
0 |
0 |
T2 |
800868 |
800836 |
0 |
0 |
T3 |
6786 |
5600 |
0 |
0 |
T4 |
97076 |
96940 |
0 |
0 |
T5 |
145828 |
145630 |
0 |
0 |
T6 |
2106 |
1972 |
0 |
0 |
T8 |
90876 |
90750 |
0 |
0 |
T10 |
28464 |
28250 |
0 |
0 |
T20 |
2200 |
2034 |
0 |
0 |
T21 |
1888 |
1788 |
0 |
0 |
IndexIsCorrect_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
825123306 |
5293737 |
0 |
0 |
T1 |
670774 |
46197 |
0 |
0 |
T2 |
800868 |
0 |
0 |
0 |
T3 |
6786 |
0 |
0 |
0 |
T4 |
97076 |
252 |
0 |
0 |
T5 |
145828 |
746 |
0 |
0 |
T6 |
2106 |
4 |
0 |
0 |
T7 |
0 |
24 |
0 |
0 |
T8 |
90876 |
19695 |
0 |
0 |
T9 |
0 |
314 |
0 |
0 |
T10 |
28464 |
124 |
0 |
0 |
T20 |
2200 |
0 |
0 |
0 |
T21 |
1888 |
0 |
0 |
0 |
T23 |
0 |
684 |
0 |
0 |
T24 |
0 |
25914 |
0 |
0 |
T44 |
0 |
25176 |
0 |
0 |
T45 |
0 |
23045 |
0 |
0 |
T46 |
0 |
23047 |
0 |
0 |
T47 |
0 |
22138 |
0 |
0 |
LockArbDecision_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
825123306 |
0 |
0 |
0 |
NoReadyValidNoGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
825123306 |
595038658 |
0 |
0 |
T1 |
670774 |
773 |
0 |
0 |
T2 |
800868 |
774462 |
0 |
0 |
T3 |
6786 |
5434 |
0 |
0 |
T4 |
97076 |
55574 |
0 |
0 |
T5 |
145828 |
21191 |
0 |
0 |
T6 |
2106 |
1883 |
0 |
0 |
T8 |
90876 |
775 |
0 |
0 |
T10 |
28464 |
15248 |
0 |
0 |
T20 |
2200 |
2002 |
0 |
0 |
T21 |
1888 |
1756 |
0 |
0 |
ReadyAndValidImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
825123306 |
5293737 |
0 |
0 |
T1 |
670774 |
46197 |
0 |
0 |
T2 |
800868 |
0 |
0 |
0 |
T3 |
6786 |
0 |
0 |
0 |
T4 |
97076 |
252 |
0 |
0 |
T5 |
145828 |
746 |
0 |
0 |
T6 |
2106 |
4 |
0 |
0 |
T7 |
0 |
24 |
0 |
0 |
T8 |
90876 |
19695 |
0 |
0 |
T9 |
0 |
314 |
0 |
0 |
T10 |
28464 |
124 |
0 |
0 |
T20 |
2200 |
0 |
0 |
0 |
T21 |
1888 |
0 |
0 |
0 |
T23 |
0 |
684 |
0 |
0 |
T24 |
0 |
25914 |
0 |
0 |
T44 |
0 |
25176 |
0 |
0 |
T45 |
0 |
23045 |
0 |
0 |
T46 |
0 |
23047 |
0 |
0 |
T47 |
0 |
22138 |
0 |
0 |
ReqAndReadyImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
825123306 |
5293737 |
0 |
0 |
T1 |
670774 |
46197 |
0 |
0 |
T2 |
800868 |
0 |
0 |
0 |
T3 |
6786 |
0 |
0 |
0 |
T4 |
97076 |
252 |
0 |
0 |
T5 |
145828 |
746 |
0 |
0 |
T6 |
2106 |
4 |
0 |
0 |
T7 |
0 |
24 |
0 |
0 |
T8 |
90876 |
19695 |
0 |
0 |
T9 |
0 |
314 |
0 |
0 |
T10 |
28464 |
124 |
0 |
0 |
T20 |
2200 |
0 |
0 |
0 |
T21 |
1888 |
0 |
0 |
0 |
T23 |
0 |
684 |
0 |
0 |
T24 |
0 |
25914 |
0 |
0 |
T44 |
0 |
25176 |
0 |
0 |
T45 |
0 |
23045 |
0 |
0 |
T46 |
0 |
23047 |
0 |
0 |
T47 |
0 |
22138 |
0 |
0 |
ReqImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
825123306 |
218501360 |
0 |
0 |
T1 |
670774 |
669763 |
0 |
0 |
T2 |
800868 |
0 |
0 |
0 |
T3 |
6786 |
0 |
0 |
0 |
T4 |
97076 |
41330 |
0 |
0 |
T5 |
145828 |
124399 |
0 |
0 |
T6 |
2106 |
53 |
0 |
0 |
T7 |
0 |
3245 |
0 |
0 |
T8 |
90876 |
89935 |
0 |
0 |
T9 |
0 |
13769 |
0 |
0 |
T10 |
28464 |
12934 |
0 |
0 |
T20 |
2200 |
0 |
0 |
0 |
T21 |
1888 |
0 |
0 |
0 |
T23 |
0 |
132455 |
0 |
0 |
T24 |
0 |
247664 |
0 |
0 |
T44 |
0 |
231353 |
0 |
0 |
T45 |
0 |
350338 |
0 |
0 |
T46 |
0 |
397916 |
0 |
0 |
T47 |
0 |
271918 |
0 |
0 |
ReqStaysHighUntilGranted0_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
825123306 |
0 |
0 |
0 |
RoundRobin_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
825123306 |
56478 |
0 |
2092 |
T1 |
670774 |
584 |
0 |
2 |
T2 |
800868 |
0 |
0 |
2 |
T3 |
6786 |
0 |
0 |
2 |
T4 |
97076 |
0 |
0 |
2 |
T5 |
145828 |
0 |
0 |
2 |
T6 |
2106 |
0 |
0 |
2 |
T8 |
90876 |
0 |
0 |
2 |
T9 |
0 |
111 |
0 |
0 |
T10 |
28464 |
0 |
0 |
2 |
T20 |
2200 |
0 |
0 |
2 |
T21 |
1888 |
0 |
0 |
2 |
T26 |
0 |
505 |
0 |
0 |
T40 |
0 |
1041 |
0 |
0 |
T41 |
0 |
566 |
0 |
0 |
T45 |
0 |
971 |
0 |
0 |
T46 |
0 |
778 |
0 |
0 |
T47 |
0 |
332 |
0 |
0 |
T69 |
0 |
604 |
0 |
0 |
T70 |
0 |
2419 |
0 |
0 |
T71 |
0 |
20 |
0 |
0 |
ValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
825123306 |
823601392 |
0 |
0 |
T1 |
670774 |
670576 |
0 |
0 |
T2 |
800868 |
800836 |
0 |
0 |
T3 |
6786 |
5600 |
0 |
0 |
T4 |
97076 |
96940 |
0 |
0 |
T5 |
145828 |
145630 |
0 |
0 |
T6 |
2106 |
1972 |
0 |
0 |
T8 |
90876 |
90750 |
0 |
0 |
T10 |
28464 |
28250 |
0 |
0 |
T20 |
2200 |
2034 |
0 |
0 |
T21 |
1888 |
1788 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random
| Line No. | Total | Covered | Percent |
TOTAL | | 52 | 48 | 92.31 |
CONT_ASSIGN | 62 | 0 | 0 | |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 174 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 182 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
ALWAYS | 191 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
62 |
|
unreachable |
112 |
4 |
4 |
118 |
4 |
4 |
122 |
0 |
4 |
126 |
4 |
4 |
128 |
4 |
4 |
148 |
3 |
3 |
150 |
3 |
3 |
151 |
3 |
3 |
155 |
3 |
3 |
156 |
3 |
3 |
160 |
3 |
3 |
161 |
3 |
3 |
163 |
1 |
1(2 unreachable) |
164 |
3 |
3 |
174 |
1 |
1 |
180 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
194 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random
| Total | Covered | Percent |
Conditions | 130 | 127 | 97.69 |
Logical | 130 | 127 | 97.69 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 118
EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T6,T8 |
1 | 0 | Covered | T1,T4,T6 |
1 | 1 | Covered | T1,T4,T6 |
LINE 118
EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T6,T8 |
1 | 0 | Covered | T1,T4,T6 |
1 | 1 | Covered | T1,T4,T6 |
LINE 118
EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T6,T8 |
1 | 0 | Covered | T1,T4,T6 |
1 | 1 | Covered | T1,T4,T6 |
LINE 118
EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T9,T45 |
1 | 1 | Covered | T1,T4,T6 |
LINE 126
EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T4,T6 |
1 | 1 | 0 | Covered | T1,T4,T6 |
1 | 1 | 1 | Covered | T1,T4,T6 |
LINE 126
EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T4,T6 |
1 | 1 | 0 | Covered | T1,T4,T6 |
1 | 1 | 1 | Covered | T1,T4,T6 |
LINE 126
EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T4,T6 |
1 | 1 | 0 | Covered | T1,T4,T6 |
1 | 1 | 1 | Covered | T1,T4,T6 |
LINE 126
EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T4,T6 |
1 | 1 | 0 | Covered | T1,T4,T6 |
1 | 1 | 1 | Covered | T1,T4,T6 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T6 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T6 |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Unreachable | |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T4,T6 |
1 | 1 | Covered | T1,T4,T6 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T6 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T6 |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T4,T6 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T4,T6 |
1 | 1 | Covered | T1,T4,T6 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T6 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T6 |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T4,T6 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T4,T6 |
1 | 1 | Covered | T1,T4,T6 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T6 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T6 |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T4,T6 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T4,T6 |
1 | 1 | Covered | T1,T4,T6 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T6 |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T6 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T6 |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T6 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T6 |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T6 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T24,T44,T46 |
1 | 0 | Covered | T24,T44,T46 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T4,T6 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T4,T6 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T24,T44,T46 |
1 | 0 | Covered | T1,T4,T6 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T8,T24 |
1 | 0 | Covered | T1,T4,T6 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T4,T6 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T4,T6 |
1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T4,T6 |
1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1- | Status | Tests |
0 | Covered | T1,T4,T6 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T4,T6 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T4,T6 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1- | Status | Tests |
0 | Covered | T1,T4,T6 |
1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T6 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T4,T6 |
1 | 1 | Covered | T1,T4,T6 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T6 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T4,T6 |
1 | 1 | Covered | T1,T2,T3 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T4,T6 |
1 | 1 | Covered | T1,T4,T6 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T8,T9 |
1 | 0 | Covered | T1,T4,T6 |
1 | 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Unreachable | |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Unreachable | |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T4,T6 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random
| Line No. | Total | Covered | Percent |
Branches |
|
22 |
22 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
IF |
191 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T4,T6 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T4,T6 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T4,T6 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T4,T6 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T4,T6 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T4,T6 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T6 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T6 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T6 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T6 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random
Assertion Details
CheckHotOne_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412561653 |
411800696 |
0 |
0 |
T1 |
335387 |
335288 |
0 |
0 |
T2 |
400434 |
400418 |
0 |
0 |
T3 |
3393 |
2800 |
0 |
0 |
T4 |
48538 |
48470 |
0 |
0 |
T5 |
72914 |
72815 |
0 |
0 |
T6 |
1053 |
986 |
0 |
0 |
T8 |
45438 |
45375 |
0 |
0 |
T10 |
14232 |
14125 |
0 |
0 |
T20 |
1100 |
1017 |
0 |
0 |
T21 |
944 |
894 |
0 |
0 |
CheckNGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1052 |
1052 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
GntImpliesReady_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412561653 |
2727140 |
0 |
0 |
T1 |
335387 |
22727 |
0 |
0 |
T2 |
400434 |
0 |
0 |
0 |
T3 |
3393 |
0 |
0 |
0 |
T4 |
48538 |
252 |
0 |
0 |
T5 |
72914 |
387 |
0 |
0 |
T6 |
1053 |
4 |
0 |
0 |
T7 |
0 |
24 |
0 |
0 |
T8 |
45438 |
8927 |
0 |
0 |
T9 |
0 |
240 |
0 |
0 |
T10 |
14232 |
0 |
0 |
0 |
T20 |
1100 |
0 |
0 |
0 |
T21 |
944 |
0 |
0 |
0 |
T23 |
0 |
684 |
0 |
0 |
T24 |
0 |
14062 |
0 |
0 |
T44 |
0 |
12644 |
0 |
0 |
GntImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412561653 |
2727140 |
0 |
0 |
T1 |
335387 |
22727 |
0 |
0 |
T2 |
400434 |
0 |
0 |
0 |
T3 |
3393 |
0 |
0 |
0 |
T4 |
48538 |
252 |
0 |
0 |
T5 |
72914 |
387 |
0 |
0 |
T6 |
1053 |
4 |
0 |
0 |
T7 |
0 |
24 |
0 |
0 |
T8 |
45438 |
8927 |
0 |
0 |
T9 |
0 |
240 |
0 |
0 |
T10 |
14232 |
0 |
0 |
0 |
T20 |
1100 |
0 |
0 |
0 |
T21 |
944 |
0 |
0 |
0 |
T23 |
0 |
684 |
0 |
0 |
T24 |
0 |
14062 |
0 |
0 |
T44 |
0 |
12644 |
0 |
0 |
GrantKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412561653 |
411800696 |
0 |
0 |
T1 |
335387 |
335288 |
0 |
0 |
T2 |
400434 |
400418 |
0 |
0 |
T3 |
3393 |
2800 |
0 |
0 |
T4 |
48538 |
48470 |
0 |
0 |
T5 |
72914 |
72815 |
0 |
0 |
T6 |
1053 |
986 |
0 |
0 |
T8 |
45438 |
45375 |
0 |
0 |
T10 |
14232 |
14125 |
0 |
0 |
T20 |
1100 |
1017 |
0 |
0 |
T21 |
944 |
894 |
0 |
0 |
IdxKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412561653 |
411800696 |
0 |
0 |
T1 |
335387 |
335288 |
0 |
0 |
T2 |
400434 |
400418 |
0 |
0 |
T3 |
3393 |
2800 |
0 |
0 |
T4 |
48538 |
48470 |
0 |
0 |
T5 |
72914 |
72815 |
0 |
0 |
T6 |
1053 |
986 |
0 |
0 |
T8 |
45438 |
45375 |
0 |
0 |
T10 |
14232 |
14125 |
0 |
0 |
T20 |
1100 |
1017 |
0 |
0 |
T21 |
944 |
894 |
0 |
0 |
IndexIsCorrect_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412561653 |
2727140 |
0 |
0 |
T1 |
335387 |
22727 |
0 |
0 |
T2 |
400434 |
0 |
0 |
0 |
T3 |
3393 |
0 |
0 |
0 |
T4 |
48538 |
252 |
0 |
0 |
T5 |
72914 |
387 |
0 |
0 |
T6 |
1053 |
4 |
0 |
0 |
T7 |
0 |
24 |
0 |
0 |
T8 |
45438 |
8927 |
0 |
0 |
T9 |
0 |
240 |
0 |
0 |
T10 |
14232 |
0 |
0 |
0 |
T20 |
1100 |
0 |
0 |
0 |
T21 |
944 |
0 |
0 |
0 |
T23 |
0 |
684 |
0 |
0 |
T24 |
0 |
14062 |
0 |
0 |
T44 |
0 |
12644 |
0 |
0 |
LockArbDecision_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412561653 |
0 |
0 |
0 |
NoReadyValidNoGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412561653 |
292683137 |
0 |
0 |
T1 |
335387 |
370 |
0 |
0 |
T2 |
400434 |
387151 |
0 |
0 |
T3 |
3393 |
2634 |
0 |
0 |
T4 |
48538 |
7104 |
0 |
0 |
T5 |
72914 |
7281 |
0 |
0 |
T6 |
1053 |
897 |
0 |
0 |
T8 |
45438 |
376 |
0 |
0 |
T10 |
14232 |
14061 |
0 |
0 |
T20 |
1100 |
985 |
0 |
0 |
T21 |
944 |
862 |
0 |
0 |
ReadyAndValidImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412561653 |
2727140 |
0 |
0 |
T1 |
335387 |
22727 |
0 |
0 |
T2 |
400434 |
0 |
0 |
0 |
T3 |
3393 |
0 |
0 |
0 |
T4 |
48538 |
252 |
0 |
0 |
T5 |
72914 |
387 |
0 |
0 |
T6 |
1053 |
4 |
0 |
0 |
T7 |
0 |
24 |
0 |
0 |
T8 |
45438 |
8927 |
0 |
0 |
T9 |
0 |
240 |
0 |
0 |
T10 |
14232 |
0 |
0 |
0 |
T20 |
1100 |
0 |
0 |
0 |
T21 |
944 |
0 |
0 |
0 |
T23 |
0 |
684 |
0 |
0 |
T24 |
0 |
14062 |
0 |
0 |
T44 |
0 |
12644 |
0 |
0 |
ReqAndReadyImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412561653 |
2727140 |
0 |
0 |
T1 |
335387 |
22727 |
0 |
0 |
T2 |
400434 |
0 |
0 |
0 |
T3 |
3393 |
0 |
0 |
0 |
T4 |
48538 |
252 |
0 |
0 |
T5 |
72914 |
387 |
0 |
0 |
T6 |
1053 |
4 |
0 |
0 |
T7 |
0 |
24 |
0 |
0 |
T8 |
45438 |
8927 |
0 |
0 |
T9 |
0 |
240 |
0 |
0 |
T10 |
14232 |
0 |
0 |
0 |
T20 |
1100 |
0 |
0 |
0 |
T21 |
944 |
0 |
0 |
0 |
T23 |
0 |
684 |
0 |
0 |
T24 |
0 |
14062 |
0 |
0 |
T44 |
0 |
12644 |
0 |
0 |
ReqImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412561653 |
113609526 |
0 |
0 |
T1 |
335387 |
334882 |
0 |
0 |
T2 |
400434 |
0 |
0 |
0 |
T3 |
3393 |
0 |
0 |
0 |
T4 |
48538 |
41330 |
0 |
0 |
T5 |
72914 |
65498 |
0 |
0 |
T6 |
1053 |
53 |
0 |
0 |
T7 |
0 |
3245 |
0 |
0 |
T8 |
45438 |
44963 |
0 |
0 |
T9 |
0 |
6873 |
0 |
0 |
T10 |
14232 |
0 |
0 |
0 |
T20 |
1100 |
0 |
0 |
0 |
T21 |
944 |
0 |
0 |
0 |
T23 |
0 |
132455 |
0 |
0 |
T24 |
0 |
123841 |
0 |
0 |
T44 |
0 |
115680 |
0 |
0 |
ReqStaysHighUntilGranted0_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412561653 |
0 |
0 |
0 |
RoundRobin_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412561653 |
32567 |
0 |
1046 |
T1 |
335387 |
169 |
0 |
1 |
T2 |
400434 |
0 |
0 |
1 |
T3 |
3393 |
0 |
0 |
1 |
T4 |
48538 |
0 |
0 |
1 |
T5 |
72914 |
0 |
0 |
1 |
T6 |
1053 |
0 |
0 |
1 |
T8 |
45438 |
0 |
0 |
1 |
T9 |
0 |
111 |
0 |
0 |
T10 |
14232 |
0 |
0 |
1 |
T20 |
1100 |
0 |
0 |
1 |
T21 |
944 |
0 |
0 |
1 |
T26 |
0 |
348 |
0 |
0 |
T40 |
0 |
447 |
0 |
0 |
T41 |
0 |
415 |
0 |
0 |
T45 |
0 |
726 |
0 |
0 |
T46 |
0 |
504 |
0 |
0 |
T47 |
0 |
124 |
0 |
0 |
T69 |
0 |
192 |
0 |
0 |
T70 |
0 |
1108 |
0 |
0 |
ValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412561653 |
411800696 |
0 |
0 |
T1 |
335387 |
335288 |
0 |
0 |
T2 |
400434 |
400418 |
0 |
0 |
T3 |
3393 |
2800 |
0 |
0 |
T4 |
48538 |
48470 |
0 |
0 |
T5 |
72914 |
72815 |
0 |
0 |
T6 |
1053 |
986 |
0 |
0 |
T8 |
45438 |
45375 |
0 |
0 |
T10 |
14232 |
14125 |
0 |
0 |
T20 |
1100 |
1017 |
0 |
0 |
T21 |
944 |
894 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random
| Line No. | Total | Covered | Percent |
TOTAL | | 52 | 48 | 92.31 |
CONT_ASSIGN | 62 | 0 | 0 | |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 174 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 182 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
ALWAYS | 191 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
62 |
|
unreachable |
112 |
4 |
4 |
118 |
4 |
4 |
122 |
0 |
4 |
126 |
4 |
4 |
128 |
4 |
4 |
148 |
3 |
3 |
150 |
3 |
3 |
151 |
3 |
3 |
155 |
3 |
3 |
156 |
3 |
3 |
160 |
3 |
3 |
161 |
3 |
3 |
163 |
1 |
1(2 unreachable) |
164 |
3 |
3 |
174 |
1 |
1 |
180 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
194 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random
| Total | Covered | Percent |
Conditions | 130 | 127 | 97.69 |
Logical | 130 | 127 | 97.69 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 118
EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T10,T8 |
1 | 0 | Covered | T1,T10,T5 |
1 | 1 | Covered | T1,T10,T5 |
LINE 118
EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T10,T8 |
1 | 0 | Covered | T1,T10,T5 |
1 | 1 | Covered | T1,T10,T5 |
LINE 118
EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T10,T8 |
1 | 0 | Covered | T1,T10,T5 |
1 | 1 | Covered | T1,T10,T5 |
LINE 118
EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T10,T5 |
1 | 0 | Covered | T1,T45,T46 |
1 | 1 | Covered | T1,T10,T5 |
LINE 126
EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T10,T5 |
1 | 1 | 0 | Covered | T1,T10,T5 |
1 | 1 | 1 | Covered | T1,T10,T5 |
LINE 126
EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T10,T5 |
1 | 1 | 0 | Covered | T1,T10,T5 |
1 | 1 | 1 | Covered | T1,T10,T5 |
LINE 126
EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T10,T5 |
1 | 1 | 0 | Covered | T1,T10,T5 |
1 | 1 | 1 | Covered | T1,T10,T5 |
LINE 126
EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T10 |
1 | 0 | 1 | Covered | T1,T10,T5 |
1 | 1 | 0 | Covered | T1,T10,T5 |
1 | 1 | 1 | Covered | T1,T10,T5 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T10,T5 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T10,T5 |
0 | 1 | Covered | T1,T10,T5 |
1 | 0 | Unreachable | |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T10,T5 |
1 | 0 | Covered | T1,T10,T5 |
1 | 1 | Covered | T1,T10,T5 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T10,T5 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T10,T5 |
0 | 1 | Covered | T1,T10,T5 |
1 | 0 | Covered | T1,T10,T5 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T10,T5 |
1 | 0 | Covered | T1,T10,T5 |
1 | 1 | Covered | T1,T10,T5 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T10,T5 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T10,T5 |
0 | 1 | Covered | T1,T10,T5 |
1 | 0 | Covered | T1,T10,T5 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T10,T5 |
1 | 0 | Covered | T1,T10,T5 |
1 | 1 | Covered | T1,T10,T5 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T10,T5 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T10,T5 |
0 | 1 | Covered | T1,T10,T5 |
1 | 0 | Covered | T1,T10,T5 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T10,T5 |
1 | 0 | Covered | T1,T10,T5 |
1 | 1 | Covered | T1,T10,T5 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T10,T5 |
0 | 1 | Covered | T1,T10,T5 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T10,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T10,T5 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T10,T5 |
0 | 1 | Covered | T1,T10,T5 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T10,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T10,T5 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T10,T5 |
0 | 1 | Covered | T1,T10,T5 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T10,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T10,T5 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T24,T44 |
1 | 0 | Covered | T1,T8,T24 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T10,T5 |
1 | 0 | Covered | T1,T10,T5 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T10,T5 |
1 | 0 | Covered | T1,T10,T5 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T24,T44 |
1 | 0 | Covered | T1,T10,T5 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T8,T9 |
1 | 0 | Covered | T1,T10,T5 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T10,T5 |
1 | 0 | Covered | T1,T10,T5 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T10,T5 |
1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T10,T5 |
1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1- | Status | Tests |
0 | Covered | T1,T10,T5 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T10,T5 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T10,T5 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1- | Status | Tests |
0 | Covered | T1,T10,T5 |
1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T10,T5 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T10,T5 |
1 | 0 | Covered | T1,T10,T5 |
1 | 1 | Covered | T1,T10,T5 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T10,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T10,T5 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T10,T5 |
1 | 1 | Covered | T1,T2,T3 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T10,T5 |
1 | 1 | Covered | T1,T10,T5 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T10,T8 |
1 | 0 | Covered | T1,T10,T5 |
1 | 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T10,T5 |
1 | 0 | Unreachable | |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T10,T5 |
1 | 0 | Unreachable | |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T10,T5 |
1 | 0 | Covered | T1,T10,T5 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random
| Line No. | Total | Covered | Percent |
Branches |
|
22 |
22 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
IF |
191 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T10,T5 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T10,T5 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T10,T5 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T10,T5 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T10,T5 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T10,T5 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T10,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T10,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T10,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T10,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random
Assertion Details
CheckHotOne_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412561653 |
411800696 |
0 |
0 |
T1 |
335387 |
335288 |
0 |
0 |
T2 |
400434 |
400418 |
0 |
0 |
T3 |
3393 |
2800 |
0 |
0 |
T4 |
48538 |
48470 |
0 |
0 |
T5 |
72914 |
72815 |
0 |
0 |
T6 |
1053 |
986 |
0 |
0 |
T8 |
45438 |
45375 |
0 |
0 |
T10 |
14232 |
14125 |
0 |
0 |
T20 |
1100 |
1017 |
0 |
0 |
T21 |
944 |
894 |
0 |
0 |
CheckNGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1052 |
1052 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
GntImpliesReady_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412561653 |
2566597 |
0 |
0 |
T1 |
335387 |
23470 |
0 |
0 |
T2 |
400434 |
0 |
0 |
0 |
T3 |
3393 |
0 |
0 |
0 |
T4 |
48538 |
0 |
0 |
0 |
T5 |
72914 |
359 |
0 |
0 |
T6 |
1053 |
0 |
0 |
0 |
T8 |
45438 |
10768 |
0 |
0 |
T9 |
0 |
74 |
0 |
0 |
T10 |
14232 |
124 |
0 |
0 |
T20 |
1100 |
0 |
0 |
0 |
T21 |
944 |
0 |
0 |
0 |
T24 |
0 |
11852 |
0 |
0 |
T44 |
0 |
12532 |
0 |
0 |
T45 |
0 |
23045 |
0 |
0 |
T46 |
0 |
23047 |
0 |
0 |
T47 |
0 |
22138 |
0 |
0 |
GntImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412561653 |
2566597 |
0 |
0 |
T1 |
335387 |
23470 |
0 |
0 |
T2 |
400434 |
0 |
0 |
0 |
T3 |
3393 |
0 |
0 |
0 |
T4 |
48538 |
0 |
0 |
0 |
T5 |
72914 |
359 |
0 |
0 |
T6 |
1053 |
0 |
0 |
0 |
T8 |
45438 |
10768 |
0 |
0 |
T9 |
0 |
74 |
0 |
0 |
T10 |
14232 |
124 |
0 |
0 |
T20 |
1100 |
0 |
0 |
0 |
T21 |
944 |
0 |
0 |
0 |
T24 |
0 |
11852 |
0 |
0 |
T44 |
0 |
12532 |
0 |
0 |
T45 |
0 |
23045 |
0 |
0 |
T46 |
0 |
23047 |
0 |
0 |
T47 |
0 |
22138 |
0 |
0 |
GrantKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412561653 |
411800696 |
0 |
0 |
T1 |
335387 |
335288 |
0 |
0 |
T2 |
400434 |
400418 |
0 |
0 |
T3 |
3393 |
2800 |
0 |
0 |
T4 |
48538 |
48470 |
0 |
0 |
T5 |
72914 |
72815 |
0 |
0 |
T6 |
1053 |
986 |
0 |
0 |
T8 |
45438 |
45375 |
0 |
0 |
T10 |
14232 |
14125 |
0 |
0 |
T20 |
1100 |
1017 |
0 |
0 |
T21 |
944 |
894 |
0 |
0 |
IdxKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412561653 |
411800696 |
0 |
0 |
T1 |
335387 |
335288 |
0 |
0 |
T2 |
400434 |
400418 |
0 |
0 |
T3 |
3393 |
2800 |
0 |
0 |
T4 |
48538 |
48470 |
0 |
0 |
T5 |
72914 |
72815 |
0 |
0 |
T6 |
1053 |
986 |
0 |
0 |
T8 |
45438 |
45375 |
0 |
0 |
T10 |
14232 |
14125 |
0 |
0 |
T20 |
1100 |
1017 |
0 |
0 |
T21 |
944 |
894 |
0 |
0 |
IndexIsCorrect_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412561653 |
2566597 |
0 |
0 |
T1 |
335387 |
23470 |
0 |
0 |
T2 |
400434 |
0 |
0 |
0 |
T3 |
3393 |
0 |
0 |
0 |
T4 |
48538 |
0 |
0 |
0 |
T5 |
72914 |
359 |
0 |
0 |
T6 |
1053 |
0 |
0 |
0 |
T8 |
45438 |
10768 |
0 |
0 |
T9 |
0 |
74 |
0 |
0 |
T10 |
14232 |
124 |
0 |
0 |
T20 |
1100 |
0 |
0 |
0 |
T21 |
944 |
0 |
0 |
0 |
T24 |
0 |
11852 |
0 |
0 |
T44 |
0 |
12532 |
0 |
0 |
T45 |
0 |
23045 |
0 |
0 |
T46 |
0 |
23047 |
0 |
0 |
T47 |
0 |
22138 |
0 |
0 |
LockArbDecision_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412561653 |
0 |
0 |
0 |
NoReadyValidNoGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412561653 |
302355521 |
0 |
0 |
T1 |
335387 |
403 |
0 |
0 |
T2 |
400434 |
387311 |
0 |
0 |
T3 |
3393 |
2800 |
0 |
0 |
T4 |
48538 |
48470 |
0 |
0 |
T5 |
72914 |
13910 |
0 |
0 |
T6 |
1053 |
986 |
0 |
0 |
T8 |
45438 |
399 |
0 |
0 |
T10 |
14232 |
1187 |
0 |
0 |
T20 |
1100 |
1017 |
0 |
0 |
T21 |
944 |
894 |
0 |
0 |
ReadyAndValidImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412561653 |
2566597 |
0 |
0 |
T1 |
335387 |
23470 |
0 |
0 |
T2 |
400434 |
0 |
0 |
0 |
T3 |
3393 |
0 |
0 |
0 |
T4 |
48538 |
0 |
0 |
0 |
T5 |
72914 |
359 |
0 |
0 |
T6 |
1053 |
0 |
0 |
0 |
T8 |
45438 |
10768 |
0 |
0 |
T9 |
0 |
74 |
0 |
0 |
T10 |
14232 |
124 |
0 |
0 |
T20 |
1100 |
0 |
0 |
0 |
T21 |
944 |
0 |
0 |
0 |
T24 |
0 |
11852 |
0 |
0 |
T44 |
0 |
12532 |
0 |
0 |
T45 |
0 |
23045 |
0 |
0 |
T46 |
0 |
23047 |
0 |
0 |
T47 |
0 |
22138 |
0 |
0 |
ReqAndReadyImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412561653 |
2566597 |
0 |
0 |
T1 |
335387 |
23470 |
0 |
0 |
T2 |
400434 |
0 |
0 |
0 |
T3 |
3393 |
0 |
0 |
0 |
T4 |
48538 |
0 |
0 |
0 |
T5 |
72914 |
359 |
0 |
0 |
T6 |
1053 |
0 |
0 |
0 |
T8 |
45438 |
10768 |
0 |
0 |
T9 |
0 |
74 |
0 |
0 |
T10 |
14232 |
124 |
0 |
0 |
T20 |
1100 |
0 |
0 |
0 |
T21 |
944 |
0 |
0 |
0 |
T24 |
0 |
11852 |
0 |
0 |
T44 |
0 |
12532 |
0 |
0 |
T45 |
0 |
23045 |
0 |
0 |
T46 |
0 |
23047 |
0 |
0 |
T47 |
0 |
22138 |
0 |
0 |
ReqImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412561653 |
104891834 |
0 |
0 |
T1 |
335387 |
334881 |
0 |
0 |
T2 |
400434 |
0 |
0 |
0 |
T3 |
3393 |
0 |
0 |
0 |
T4 |
48538 |
0 |
0 |
0 |
T5 |
72914 |
58901 |
0 |
0 |
T6 |
1053 |
0 |
0 |
0 |
T8 |
45438 |
44972 |
0 |
0 |
T9 |
0 |
6896 |
0 |
0 |
T10 |
14232 |
12934 |
0 |
0 |
T20 |
1100 |
0 |
0 |
0 |
T21 |
944 |
0 |
0 |
0 |
T24 |
0 |
123823 |
0 |
0 |
T44 |
0 |
115673 |
0 |
0 |
T45 |
0 |
350338 |
0 |
0 |
T46 |
0 |
397916 |
0 |
0 |
T47 |
0 |
271918 |
0 |
0 |
ReqStaysHighUntilGranted0_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412561653 |
0 |
0 |
0 |
RoundRobin_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412561653 |
23911 |
0 |
1046 |
T1 |
335387 |
415 |
0 |
1 |
T2 |
400434 |
0 |
0 |
1 |
T3 |
3393 |
0 |
0 |
1 |
T4 |
48538 |
0 |
0 |
1 |
T5 |
72914 |
0 |
0 |
1 |
T6 |
1053 |
0 |
0 |
1 |
T8 |
45438 |
0 |
0 |
1 |
T10 |
14232 |
0 |
0 |
1 |
T20 |
1100 |
0 |
0 |
1 |
T21 |
944 |
0 |
0 |
1 |
T26 |
0 |
157 |
0 |
0 |
T40 |
0 |
594 |
0 |
0 |
T41 |
0 |
151 |
0 |
0 |
T45 |
0 |
245 |
0 |
0 |
T46 |
0 |
274 |
0 |
0 |
T47 |
0 |
208 |
0 |
0 |
T69 |
0 |
412 |
0 |
0 |
T70 |
0 |
1311 |
0 |
0 |
T71 |
0 |
20 |
0 |
0 |
ValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
412561653 |
411800696 |
0 |
0 |
T1 |
335387 |
335288 |
0 |
0 |
T2 |
400434 |
400418 |
0 |
0 |
T3 |
3393 |
2800 |
0 |
0 |
T4 |
48538 |
48470 |
0 |
0 |
T5 |
72914 |
72815 |
0 |
0 |
T6 |
1053 |
986 |
0 |
0 |
T8 |
45438 |
45375 |
0 |
0 |
T10 |
14232 |
14125 |
0 |
0 |
T20 |
1100 |
1017 |
0 |
0 |
T21 |
944 |
894 |
0 |
0 |