Module Definition
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Module : prim_subreg
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr20_field2 60.48 71.43 50.00 60.00
tb.dut.u_reg_core.u_status_init_wip 65.24 85.71 50.00 60.00
tb.dut.u_reg_core.u_status_initialized 65.24 85.71 50.00 60.00
tb.dut.u_reg_core.u_std_fault_status_storage_err 65.24 85.71 50.00 60.00
tb.dut.u_reg_core.u_phy_alert_cfg_alert_ack 65.24 85.71 50.00 60.00
tb.dut.u_reg_core.u_phy_alert_cfg_alert_trig 65.24 85.71 50.00 60.00
tb.dut.u_reg_core.u_phy_status_init_wip 65.24 85.71 50.00 60.00
tb.dut.u_reg_core.u_phy_status_prog_normal_avail 65.24 85.71 50.00 60.00
tb.dut.u_reg_core.u_phy_status_prog_repair_avail 65.24 85.71 50.00 60.00
tb.dut.u_reg_core.u_intr_state_prog_empty 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_intr_state_prog_lvl 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_intr_state_rd_full 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_intr_state_rd_lvl 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_intr_state_op_done 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_intr_state_corr_err 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_intr_enable_prog_empty 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_intr_enable_prog_lvl 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_intr_enable_rd_full 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_intr_enable_rd_lvl 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_intr_enable_op_done 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_intr_enable_corr_err 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_dis 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_exec 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_init 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_control_start 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_control_op 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_control_prog_sel 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_control_erase_sel 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_control_partition_sel 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_control_info_sel 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_control_num 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_addr 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_prog_type_en_normal 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_prog_type_en_repair 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_erase_suspend 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_1 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_2 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_3 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_4 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_5 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_6 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_7 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_0_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_0_rd_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_0_prog_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_0_erase_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_0_scramble_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_0_ecc_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_0_he_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_1_en_1 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_1_rd_en_1 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_1_prog_en_1 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_1_erase_en_1 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_1_scramble_en_1 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_1_ecc_en_1 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_1_he_en_1 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_2_en_2 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_2_rd_en_2 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_2_prog_en_2 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_2_erase_en_2 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_2_scramble_en_2 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_2_ecc_en_2 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_2_he_en_2 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_3_en_3 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_3_rd_en_3 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_3_prog_en_3 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_3_erase_en_3 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_3_scramble_en_3 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_3_ecc_en_3 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_3_he_en_3 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_4_en_4 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_4_rd_en_4 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_4_prog_en_4 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_4_erase_en_4 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_4_scramble_en_4 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_4_ecc_en_4 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_4_he_en_4 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_5_en_5 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_5_rd_en_5 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_5_prog_en_5 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_5_erase_en_5 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_5_scramble_en_5 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_5_ecc_en_5 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_5_he_en_5 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_6_en_6 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_6_rd_en_6 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_6_prog_en_6 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_6_erase_en_6 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_6_scramble_en_6 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_6_ecc_en_6 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_6_he_en_6 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_7_en_7 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_7_rd_en_7 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_7_prog_en_7 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_7_erase_en_7 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_7_scramble_en_7 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_7_ecc_en_7 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_7_he_en_7 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_0_base_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_0_size_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_1_base_1 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_1_size_1 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_2_base_2 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_2_size_2 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_3_base_3 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_3_size_3 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_4_base_4 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_4_size_4 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_5_base_5 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_5_size_5 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_6_base_6 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_6_size_6 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_7_base_7 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_7_size_7 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_default_region_rd_en 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_default_region_prog_en 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_default_region_erase_en 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_default_region_scramble_en 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_default_region_ecc_en 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_default_region_he_en 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_1 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_2 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_3 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_4 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_5 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_6 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_7 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_8 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_9 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_0_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_0_rd_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_0_prog_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_0_erase_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_0_scramble_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_0_ecc_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_0_he_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_1_en_1 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_1_rd_en_1 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_1_prog_en_1 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_1_erase_en_1 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_1_scramble_en_1 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_1_ecc_en_1 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_1_he_en_1 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_2_en_2 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_2_rd_en_2 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_2_prog_en_2 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_2_erase_en_2 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_2_scramble_en_2 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_2_ecc_en_2 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_2_he_en_2 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_3_en_3 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_3_rd_en_3 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_3_prog_en_3 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_3_erase_en_3 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_3_scramble_en_3 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_3_ecc_en_3 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_3_he_en_3 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_4_en_4 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_4_rd_en_4 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_4_prog_en_4 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_4_erase_en_4 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_4_scramble_en_4 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_4_ecc_en_4 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_4_he_en_4 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_5_en_5 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_5_rd_en_5 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_5_prog_en_5 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_5_erase_en_5 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_5_scramble_en_5 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_5_ecc_en_5 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_5_he_en_5 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_6_en_6 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_6_rd_en_6 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_6_prog_en_6 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_6_erase_en_6 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_6_scramble_en_6 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_6_ecc_en_6 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_6_he_en_6 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_7_en_7 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_7_rd_en_7 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_7_prog_en_7 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_7_erase_en_7 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_7_scramble_en_7 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_7_ecc_en_7 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_7_he_en_7 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_8_en_8 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_8_rd_en_8 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_8_prog_en_8 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_8_erase_en_8 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_8_scramble_en_8 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_8_ecc_en_8 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_8_he_en_8 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_9_en_9 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_9_rd_en_9 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_9_prog_en_9 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_9_erase_en_9 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_9_scramble_en_9 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_9_ecc_en_9 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_9_he_en_9 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info1_regwen 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info1_page_cfg_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info1_page_cfg_rd_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info1_page_cfg_prog_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info1_page_cfg_erase_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info1_page_cfg_scramble_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info1_page_cfg_ecc_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info1_page_cfg_he_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_regwen_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_regwen_1 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_0_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_0_rd_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_0_prog_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_0_erase_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_0_scramble_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_0_ecc_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_0_he_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_1_en_1 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_1_rd_en_1 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_1_prog_en_1 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_1_erase_en_1 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_1_scramble_en_1 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_1_ecc_en_1 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_1_he_en_1 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_1 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_2 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_3 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_4 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_5 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_6 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_7 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_8 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_9 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_0_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_0_rd_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_0_prog_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_0_erase_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_0_scramble_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_0_ecc_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_0_he_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_1_en_1 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_1_rd_en_1 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_1_prog_en_1 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_1_erase_en_1 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_1_scramble_en_1 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_1_ecc_en_1 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_1_he_en_1 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_2_en_2 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_2_rd_en_2 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_2_prog_en_2 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_2_erase_en_2 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_2_scramble_en_2 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_2_ecc_en_2 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_2_he_en_2 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_3_en_3 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_3_rd_en_3 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_3_prog_en_3 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_3_erase_en_3 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_3_scramble_en_3 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_3_ecc_en_3 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_3_he_en_3 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_4_en_4 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_4_rd_en_4 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_4_prog_en_4 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_4_erase_en_4 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_4_scramble_en_4 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_4_ecc_en_4 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_4_he_en_4 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_5_en_5 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_5_rd_en_5 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_5_prog_en_5 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_5_erase_en_5 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_5_scramble_en_5 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_5_ecc_en_5 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_5_he_en_5 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_6_en_6 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_6_rd_en_6 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_6_prog_en_6 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_6_erase_en_6 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_6_scramble_en_6 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_6_ecc_en_6 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_6_he_en_6 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_7_en_7 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_7_rd_en_7 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_7_prog_en_7 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_7_erase_en_7 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_7_scramble_en_7 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_7_ecc_en_7 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_7_he_en_7 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_8_en_8 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_8_rd_en_8 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_8_prog_en_8 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_8_erase_en_8 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_8_scramble_en_8 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_8_ecc_en_8 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_8_he_en_8 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_9_en_9 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_9_rd_en_9 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_9_prog_en_9 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_9_erase_en_9 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_9_scramble_en_9 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_9_ecc_en_9 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_9_he_en_9 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_regwen 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_rd_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_prog_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_erase_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_scramble_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_ecc_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_he_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_regwen_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_regwen_1 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_0_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_0_rd_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_0_prog_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_0_erase_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_0_scramble_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_0_ecc_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_0_he_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_1_en_1 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_1_rd_en_1 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_1_prog_en_1 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_1_erase_en_1 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_1_scramble_en_1 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_1_ecc_en_1 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_1_he_en_1 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_hw_info_cfg_override_scramble_dis 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_hw_info_cfg_override_ecc_dis 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank_cfg_regwen 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.staged_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.shadow_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.committed_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.staged_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.shadow_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.committed_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_op_status_done 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_op_status_err 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_status_rd_full 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_status_rd_empty 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_status_prog_full 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_status_prog_empty 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_err_code_op_err 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_err_code_mp_err 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_err_code_rd_err 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_err_code_prog_err 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_err_code_prog_win_err 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_err_code_prog_type_err 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_err_code_update_err 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_err_code_macro_err 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_std_fault_status_reg_intg_err 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_std_fault_status_prog_intg_err 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_std_fault_status_lcmgr_err 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_std_fault_status_lcmgr_intg_err 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_std_fault_status_arb_fsm_err 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_std_fault_status_phy_fsm_err 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_std_fault_status_ctrl_cnt_err 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_std_fault_status_fifo_err 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_fault_status_op_err 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_fault_status_mp_err 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_fault_status_rd_err 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_fault_status_prog_err 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_fault_status_prog_win_err 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_fault_status_prog_type_err 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_fault_status_seed_err 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_fault_status_phy_relbl_err 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_fault_status_phy_storage_err 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_fault_status_spurious_ack 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_fault_status_arb_err 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_fault_status_host_gnt_err 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_err_addr 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_ecc_single_err_cnt_ecc_single_err_cnt_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_ecc_single_err_cnt_ecc_single_err_cnt_1 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_ecc_single_err_addr_0 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_ecc_single_err_addr_1 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_scratch 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_fifo_lvl_prog 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_fifo_lvl_rd 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_fifo_rst 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr0_regwen 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr1_field0 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr1_field1 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field0 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field1 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field2 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field3 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field4 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field5 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field6 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field7 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field0 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field1 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field2 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field3 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field4 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field5 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field6 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field7 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field8 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field9 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr4_field0 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr4_field1 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr4_field2 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr4_field3 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr5_field0 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr5_field1 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr5_field2 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr5_field3 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr5_field4 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field0 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field1 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field2 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field3 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field4 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field5 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field6 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field7 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field8 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr7_field0 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr7_field1 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr8 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr9 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr10 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr11 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr12 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr13_field0 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr13_field1 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr14_field0 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr14_field1 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr15_field0 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr15_field1 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr16_field0 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr16_field1 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr17_field0 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr17_field1 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr18 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr19 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr20_field0 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr20_field1 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_subreg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Module : prim_subreg ( parameter DW=4,SwAccess=4,RESVAL=9,Mubi=1 + DW=4,SwAccess=0,RESVAL,Mubi )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_dis

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_0_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_0_rd_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_0_prog_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_0_erase_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_0_scramble_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_0_ecc_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_0_he_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_1_en_1

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_1_rd_en_1

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_1_prog_en_1

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_1_erase_en_1

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_1_scramble_en_1

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_1_ecc_en_1

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_1_he_en_1

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_2_en_2

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_2_rd_en_2

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_2_prog_en_2

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_2_erase_en_2

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_2_scramble_en_2

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_2_ecc_en_2

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_2_he_en_2

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_3_en_3

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_3_rd_en_3

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_3_prog_en_3

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_3_erase_en_3

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_3_scramble_en_3

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_3_ecc_en_3

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_3_he_en_3

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_4_en_4

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_4_rd_en_4

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_4_prog_en_4

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_4_erase_en_4

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_4_scramble_en_4

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_4_ecc_en_4

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_4_he_en_4

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_5_en_5

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_5_rd_en_5

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_5_prog_en_5

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_5_erase_en_5

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_5_scramble_en_5

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_5_ecc_en_5

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_5_he_en_5

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_6_en_6

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_6_rd_en_6

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_6_prog_en_6

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_6_erase_en_6

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_6_scramble_en_6

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_6_ecc_en_6

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_6_he_en_6

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_7_en_7

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_7_rd_en_7

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_7_prog_en_7

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_7_erase_en_7

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_7_scramble_en_7

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_7_ecc_en_7

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_7_he_en_7

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_default_region_rd_en

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_default_region_prog_en

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_default_region_erase_en

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_default_region_scramble_en

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_default_region_ecc_en

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_default_region_he_en

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_0_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_0_rd_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_0_prog_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_0_erase_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_0_scramble_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_0_ecc_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_0_he_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_1_en_1

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_1_rd_en_1

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_1_prog_en_1

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_1_erase_en_1

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_1_scramble_en_1

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_1_ecc_en_1

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_1_he_en_1

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_2_en_2

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_2_rd_en_2

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_2_prog_en_2

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_2_erase_en_2

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_2_scramble_en_2

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_2_ecc_en_2

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_2_he_en_2

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_3_en_3

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_3_rd_en_3

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_3_prog_en_3

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_3_erase_en_3

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_3_scramble_en_3

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_3_ecc_en_3

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_3_he_en_3

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_4_en_4

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_4_rd_en_4

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_4_prog_en_4

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_4_erase_en_4

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_4_scramble_en_4

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_4_ecc_en_4

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_4_he_en_4

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_5_en_5

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_5_rd_en_5

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_5_prog_en_5

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_5_erase_en_5

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_5_scramble_en_5

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_5_ecc_en_5

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_5_he_en_5

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_6_en_6

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_6_rd_en_6

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_6_prog_en_6

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_6_erase_en_6

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_6_scramble_en_6

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_6_ecc_en_6

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_6_he_en_6

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_7_en_7

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_7_rd_en_7

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_7_prog_en_7

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_7_erase_en_7

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_7_scramble_en_7

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_7_ecc_en_7

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_7_he_en_7

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_8_en_8

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_8_rd_en_8

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_8_prog_en_8

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_8_erase_en_8

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_8_scramble_en_8

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_8_ecc_en_8

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_8_he_en_8

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_9_en_9

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_9_rd_en_9

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_9_prog_en_9

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_9_erase_en_9

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_9_scramble_en_9

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_9_ecc_en_9

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_9_he_en_9

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info1_page_cfg_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info1_page_cfg_rd_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info1_page_cfg_prog_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info1_page_cfg_erase_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info1_page_cfg_scramble_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info1_page_cfg_ecc_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info1_page_cfg_he_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_0_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_0_rd_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_0_prog_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_0_erase_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_0_scramble_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_0_ecc_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_0_he_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_1_en_1

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_1_rd_en_1

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_1_prog_en_1

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_1_erase_en_1

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_1_scramble_en_1

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_1_ecc_en_1

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_1_he_en_1

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_0_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_0_rd_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_0_prog_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_0_erase_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_0_scramble_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_0_ecc_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_0_he_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_1_en_1

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_1_rd_en_1

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_1_prog_en_1

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_1_erase_en_1

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_1_scramble_en_1

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_1_ecc_en_1

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_1_he_en_1

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_2_en_2

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_2_rd_en_2

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_2_prog_en_2

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_2_erase_en_2

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_2_scramble_en_2

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_2_ecc_en_2

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_2_he_en_2

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_3_en_3

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_3_rd_en_3

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_3_prog_en_3

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_3_erase_en_3

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_3_scramble_en_3

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_3_ecc_en_3

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_3_he_en_3

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_4_en_4

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_4_rd_en_4

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_4_prog_en_4

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_4_erase_en_4

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_4_scramble_en_4

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_4_ecc_en_4

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_4_he_en_4

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_5_en_5

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_5_rd_en_5

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_5_prog_en_5

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_5_erase_en_5

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_5_scramble_en_5

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_5_ecc_en_5

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_5_he_en_5

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_6_en_6

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_6_rd_en_6

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_6_prog_en_6

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_6_erase_en_6

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_6_scramble_en_6

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_6_ecc_en_6

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_6_he_en_6

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_7_en_7

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_7_rd_en_7

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_7_prog_en_7

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_7_erase_en_7

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_7_scramble_en_7

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_7_ecc_en_7

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_7_he_en_7

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_8_en_8

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_8_rd_en_8

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_8_prog_en_8

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_8_erase_en_8

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_8_scramble_en_8

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_8_ecc_en_8

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_8_he_en_8

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_9_en_9

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_9_rd_en_9

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_9_prog_en_9

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_9_erase_en_9

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_9_scramble_en_9

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_9_ecc_en_9

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_9_he_en_9

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_rd_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_prog_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_erase_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_scramble_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_ecc_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_he_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_0_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_0_rd_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_0_prog_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_0_erase_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_0_scramble_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_0_ecc_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_0_he_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_1_en_1

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_1_rd_en_1

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_1_prog_en_1

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_1_erase_en_1

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_1_scramble_en_1

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_1_ecc_en_1

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_1_he_en_1

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_hw_info_cfg_override_scramble_dis

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_hw_info_cfg_override_ecc_dis

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field0

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field1

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr5_field4

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT16,T48,T49
1CoveredT16,T48,T49

Cond Coverage for Module : prim_subreg ( parameter DW=20,SwAccess=0,RESVAL=0,Mubi=0 + DW=20,SwAccess=1,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_addr

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr13_field0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_err_addr

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_ecc_single_err_addr_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_ecc_single_err_addr_1

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT16,T48,T49
1CoveredT48,T49,T50

Cond Coverage for Module : prim_subreg ( parameter DW=1,SwAccess=3,RESVAL=0,Mubi=0 + DW=1,SwAccess=0,RESVAL,Mubi=0 + DW=1,SwAccess=4,RESVAL=0,Mubi=0 + DW=1,SwAccess=5,RESVAL=1,Mubi=0 + DW=1,SwAccess=1,RESVAL,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_intr_state_prog_empty

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_intr_state_prog_lvl

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_intr_state_rd_full

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_intr_state_rd_lvl

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_intr_state_op_done

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_intr_state_corr_err

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_err_code_op_err

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_err_code_mp_err

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_err_code_rd_err

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_err_code_prog_err

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_err_code_prog_win_err

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_err_code_prog_type_err

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_err_code_update_err

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_err_code_macro_err

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field0

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field1

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field2

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field4

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field5

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field6

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr20_field0

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr20_field1

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_intr_enable_prog_empty

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_intr_enable_prog_lvl

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_intr_enable_rd_full

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_intr_enable_rd_lvl

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_intr_enable_op_done

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_intr_enable_corr_err

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_control_start

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_control_prog_sel

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_control_erase_sel

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_control_partition_sel

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_erase_suspend

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.staged_reg

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.shadow_reg

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.committed_reg

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.staged_reg

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.shadow_reg

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.committed_reg

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_op_status_done

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_op_status_err

SCORECOND
65.24 50.00
tb.dut.u_reg_core.u_phy_alert_cfg_alert_ack

SCORECOND
65.24 50.00
tb.dut.u_reg_core.u_phy_alert_cfg_alert_trig

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_fifo_rst

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field3

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field7

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field6

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field7

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field8

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr13_field1

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr14_field1

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr15_field1

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr16_field1

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr17_field1

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr18

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr19

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_init

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_prog_type_en_normal

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_prog_type_en_repair

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_1

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_2

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_3

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_4

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_5

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_6

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_7

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_1

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_2

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_3

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_4

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_5

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_6

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_7

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_8

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_9

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info1_regwen

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_regwen_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_regwen_1

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_1

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_2

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_3

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_4

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_5

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_6

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_7

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_8

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_9

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_regwen

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_regwen_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_regwen_1

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank_cfg_regwen

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr0_regwen

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_status_rd_full

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_status_rd_empty

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_status_prog_full

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_status_prog_empty

SCORECOND
65.24 50.00
tb.dut.u_reg_core.u_status_init_wip

SCORECOND
65.24 50.00
tb.dut.u_reg_core.u_status_initialized

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_std_fault_status_reg_intg_err

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_std_fault_status_prog_intg_err

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_std_fault_status_lcmgr_err

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_std_fault_status_lcmgr_intg_err

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_std_fault_status_arb_fsm_err

SCORECOND
65.24 50.00
tb.dut.u_reg_core.u_std_fault_status_storage_err

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_std_fault_status_phy_fsm_err

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_std_fault_status_ctrl_cnt_err

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_std_fault_status_fifo_err

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_fault_status_op_err

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_fault_status_mp_err

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_fault_status_rd_err

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_fault_status_prog_err

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_fault_status_prog_win_err

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_fault_status_prog_type_err

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_fault_status_seed_err

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_fault_status_phy_relbl_err

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_fault_status_phy_storage_err

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_fault_status_spurious_ack

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_fault_status_arb_err

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_fault_status_host_gnt_err

SCORECOND
65.24 50.00
tb.dut.u_reg_core.u_phy_status_init_wip

SCORECOND
65.24 50.00
tb.dut.u_reg_core.u_phy_status_prog_normal_avail

SCORECOND
65.24 50.00
tb.dut.u_reg_core.u_phy_status_prog_repair_avail

SCORECOND
60.48 50.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr20_field2

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT16,T48,T49
1CoveredT48,T49,T50

Cond Coverage for Module : prim_subreg ( parameter DW=8,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_ecc_single_err_cnt_ecc_single_err_cnt_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_ecc_single_err_cnt_ecc_single_err_cnt_1

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr1_field0

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field2

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr7_field0

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr14_field0

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr15_field0

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr16_field0

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr17_field0

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT16,T48,T49
1CoveredT48,T49,T50

Cond Coverage for Module : prim_subreg ( parameter DW=32,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_exec

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_scratch

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr8

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr9

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr10

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr11

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT16,T48,T49
1CoveredT48,T49,T50

Cond Coverage for Module : prim_subreg ( parameter DW=2,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_control_op

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_control_info_sel

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field8

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field9

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr5_field1

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field4

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field5

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field6

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT16,T48,T49
1CoveredT48,T49,T50

Cond Coverage for Module : prim_subreg ( parameter DW=10,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_0_size_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_1_size_1

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_2_size_2

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_3_size_3

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_4_size_4

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_5_size_5

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_6_size_6

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_7_size_7

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr12

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT16,T48,T49
1CoveredT16,T48,T49

Cond Coverage for Module : prim_subreg ( parameter DW=3,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field2

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field3

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field4

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field5

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field7

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr4_field0

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr4_field1

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr4_field2

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr4_field3

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr5_field0

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field0

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field1

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field3

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT16,T48,T49
1CoveredT48,T49,T195

Cond Coverage for Module : prim_subreg ( parameter DW=12,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_control_num

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT16,T48,T49
1CoveredT48,T49,T50

Cond Coverage for Module : prim_subreg ( parameter DW=5,SwAccess=0,RESVAL,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_fifo_lvl_prog

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_fifo_lvl_rd

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr1_field1

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr5_field3

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT16,T48,T49
1CoveredT48,T49,T50

Cond Coverage for Module : prim_subreg ( parameter DW=9,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_0_base_0

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_1_base_1

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_2_base_2

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_3_base_3

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_4_base_4

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_5_base_5

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_6_base_6

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_7_base_7

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr5_field2

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr7_field1

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT16,T48,T49
1CoveredT16,T48,T49

Branch Coverage for Module : prim_subreg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T48,T49,T50
0 Covered T16,T48,T49


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T16,T48,T49
0 1 Covered T48,T49,T50
0 0 Covered T16,T48,T49

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%