Module Definition
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Module Instance : tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.27 100.00 73.08 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.88 100.00 87.50 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.86 100.00 99.43 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.27 100.00 73.08 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.88 100.00 87.50 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.86 100.00 99.43 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_subreg_shadow
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Module : prim_subreg_shadow
TotalCoveredPercent
Conditions261973.08
Logical261973.08
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT16,T48,T49
10Not Covered
11CoveredT48,T49,T50

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT16,T48,T49
01Not Covered
10CoveredT48,T49,T50

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT16,T48,T49
101CoveredT48,T49,T50
110Not Covered
111CoveredT48,T49,T50

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT16,T48,T49
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT48,T49,T50
1011CoveredT48,T49,T50
1101Not Covered
1110Not Covered
1111CoveredT48,T49,T50

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT48,T49,T50
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT16,T48,T49
1CoveredT48,T49,T50

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT16,T48,T49
1CoveredT48,T49,T50

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT48,T49,T50
10CoveredT48,T49,T50
11Not Covered

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT16,T48,T49
1Not Covered

Branch Coverage for Module : prim_subreg_shadow
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T48,T49,T50
0 Covered T16,T48,T49


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T48,T49
0 1 - Covered T48,T49,T50
0 0 1 Covered T48,T49,T50
0 0 0 Covered T16,T48,T49


Assert Coverage for Module : prim_subreg_shadow
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 2518 2518 0 0
MubiIsNotYetSupported_A 830076298 828389832 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2518 2518 0 0
T16 2 2 0 0
T48 2 2 0 0
T49 2 2 0 0
T51 2 2 0 0
T52 2 2 0 0
T53 2 2 0 0
T54 2 2 0 0
T55 2 2 0 0
T56 2 2 0 0
T57 2 2 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 830076298 828389832 0 0
T16 2428 2240 0 0
T48 136808 127878 0 0
T49 5864 5680 0 0
T51 2068 1942 0 0
T52 2314 2144 0 0
T53 6430 6276 0 0
T54 8238 8126 0 0
T55 1920 1736 0 0
T56 2226 2126 0 0
T57 2782 2666 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Instance : tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0
TotalCoveredPercent
Conditions261973.08
Logical261973.08
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT16,T48,T49
10Not Covered
11CoveredT48,T49,T50

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT16,T48,T49
01Not Covered
10CoveredT48,T49,T50

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT16,T48,T49
101CoveredT48,T49,T50
110Not Covered
111CoveredT48,T49,T50

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT16,T48,T49
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT48,T49,T50
1011CoveredT48,T49,T50
1101Not Covered
1110Not Covered
1111CoveredT48,T49,T50

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT48,T49,T50
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT16,T48,T49
1CoveredT48,T49,T50

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT16,T48,T49
1CoveredT48,T49,T50

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT48,T49,T50
10CoveredT48,T49,T50
11Not Covered

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT16,T48,T49
1Not Covered

Branch Coverage for Instance : tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T48,T49,T50
0 Covered T16,T48,T49


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T48,T49
0 1 - Covered T48,T49,T50
0 0 1 Covered T48,T49,T50
0 0 0 Covered T16,T48,T49


Assert Coverage for Instance : tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1259 1259 0 0
MubiIsNotYetSupported_A 415038149 414194916 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1259 1259 0 0
T16 1 1 0 0
T48 1 1 0 0
T49 1 1 0 0
T51 1 1 0 0
T52 1 1 0 0
T53 1 1 0 0
T54 1 1 0 0
T55 1 1 0 0
T56 1 1 0 0
T57 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 415038149 414194916 0 0
T16 1214 1120 0 0
T48 68404 63939 0 0
T49 2932 2840 0 0
T51 1034 971 0 0
T52 1157 1072 0 0
T53 3215 3138 0 0
T54 4119 4063 0 0
T55 960 868 0 0
T56 1113 1063 0 0
T57 1391 1333 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Instance : tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1
TotalCoveredPercent
Conditions261973.08
Logical261973.08
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT16,T48,T49
10Not Covered
11CoveredT48,T49,T50

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT16,T48,T49
01Not Covered
10CoveredT48,T49,T50

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT16,T48,T49
101CoveredT48,T49,T50
110Not Covered
111CoveredT48,T49,T50

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT16,T48,T49
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT48,T49,T50
1011CoveredT48,T49,T50
1101Not Covered
1110Not Covered
1111CoveredT48,T49,T50

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT48,T49,T50
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT16,T48,T49
1CoveredT48,T49,T50

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT16,T48,T49
1CoveredT48,T49,T50

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT48,T49,T50
10CoveredT48,T49,T50
11Not Covered

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT16,T48,T49
1Not Covered

Branch Coverage for Instance : tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T48,T49,T50
0 Covered T16,T48,T49


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T48,T49
0 1 - Covered T48,T49,T50
0 0 1 Covered T48,T49,T50
0 0 0 Covered T16,T48,T49


Assert Coverage for Instance : tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1259 1259 0 0
MubiIsNotYetSupported_A 415038149 414194916 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1259 1259 0 0
T16 1 1 0 0
T48 1 1 0 0
T49 1 1 0 0
T51 1 1 0 0
T52 1 1 0 0
T53 1 1 0 0
T54 1 1 0 0
T55 1 1 0 0
T56 1 1 0 0
T57 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 415038149 414194916 0 0
T16 1214 1120 0 0
T48 68404 63939 0 0
T49 2932 2840 0 0
T51 1034 971 0 0
T52 1157 1072 0 0
T53 3215 3138 0 0
T54 4119 4063 0 0
T55 960 868 0 0
T56 1113 1063 0 0
T57 1391 1333 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%