Unified Coverage Report :: Module Instance :: tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	415038073	35188793	0	0
DepthKnown_A	415038073	414194840	0	0
RvalidKnown_A	415038073	414194840	0	0
WreadyKnown_A	415038073	414194840	0	0
gen_passthru_fifo.paramCheckPass	1259	1259	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415038073	35188793	0	0
T16	1214	103	0	0
T48	68404	8561	0	0
T49	2932	2101	0	0
T51	1034	18	0	0
T52	1157	19	0	0
T53	3215	1739	0	0
T54	4119	2498	0	0
T55	960	17	0	0
T56	1113	12	0	0
T57	1391	57	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415038073	414194840	0	0
T16	1214	1120	0	0
T48	68404	63939	0	0
T49	2932	2840	0	0
T51	1034	971	0	0
T52	1157	1072	0	0
T53	3215	3138	0	0
T54	4119	4063	0	0
T55	960	868	0	0
T56	1113	1063	0	0
T57	1391	1333	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415038073	414194840	0	0
T16	1214	1120	0	0
T48	68404	63939	0	0
T49	2932	2840	0	0
T51	1034	971	0	0
T52	1157	1072	0	0
T53	3215	3138	0	0
T54	4119	4063	0	0
T55	960	868	0	0
T56	1113	1063	0	0
T57	1391	1333	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415038073	414194840	0	0
T16	1214	1120	0	0
T48	68404	63939	0	0
T49	2932	2840	0	0
T51	1034	971	0	0
T52	1157	1072	0	0
T53	3215	3138	0	0
T54	4119	4063	0	0
T55	960	868	0	0
T56	1113	1063	0	0
T57	1391	1333	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1259	1259	0	0
T16	1	1	0	0
T48	1	1	0	0
T49	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	415038073	36958194	0	0
DepthKnown_A	415038073	414194840	0	0
RvalidKnown_A	415038073	414194840	0	0
WreadyKnown_A	415038073	414194840	0	0
gen_passthru_fifo.paramCheckPass	1259	1259	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415038073	36958194	0	0
T16	1214	103	0	0
T48	68404	7932	0	0
T49	2932	1127	0	0
T51	1034	18	0	0
T52	1157	19	0	0
T53	3215	921	0	0
T54	4119	1301	0	0
T55	960	17	0	0
T56	1113	62	0	0
T57	1391	57	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415038073	414194840	0	0
T16	1214	1120	0	0
T48	68404	63939	0	0
T49	2932	2840	0	0
T51	1034	971	0	0
T52	1157	1072	0	0
T53	3215	3138	0	0
T54	4119	4063	0	0
T55	960	868	0	0
T56	1113	1063	0	0
T57	1391	1333	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415038073	414194840	0	0
T16	1214	1120	0	0
T48	68404	63939	0	0
T49	2932	2840	0	0
T51	1034	971	0	0
T52	1157	1072	0	0
T53	3215	3138	0	0
T54	4119	4063	0	0
T55	960	868	0	0
T56	1113	1063	0	0
T57	1391	1333	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415038073	414194840	0	0
T16	1214	1120	0	0
T48	68404	63939	0	0
T49	2932	2840	0	0
T51	1034	971	0	0
T52	1157	1072	0	0
T53	3215	3138	0	0
T54	4119	4063	0	0
T55	960	868	0	0
T56	1113	1063	0	0
T57	1391	1333	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1259	1259	0	0
T16	1	1	0	0
T48	1	1	0	0
T49	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	415038073	7738100	0	0
DepthKnown_A	415038073	414194840	0	0
RvalidKnown_A	415038073	414194840	0	0
WreadyKnown_A	415038073	414194840	0	0
gen_passthru_fifo.paramCheckPass	1259	1259	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415038073	7738100	0	0
T49	2932	244	0	0
T51	1034	0	0	0
T52	1157	0	0	0
T53	3215	124	0	0
T54	4119	105	0	0
T55	960	0	0	0
T56	1113	0	0	0
T57	1391	0	0	0
T137	752	0	0	0
T138	3089	163	0	0
T139	0	302	0	0
T140	0	90	0	0
T141	0	129	0	0
T142	0	197	0	0
T143	0	16	0	0
T144	0	409	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415038073	414194840	0	0
T16	1214	1120	0	0
T48	68404	63939	0	0
T49	2932	2840	0	0
T51	1034	971	0	0
T52	1157	1072	0	0
T53	3215	3138	0	0
T54	4119	4063	0	0
T55	960	868	0	0
T56	1113	1063	0	0
T57	1391	1333	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415038073	414194840	0	0
T16	1214	1120	0	0
T48	68404	63939	0	0
T49	2932	2840	0	0
T51	1034	971	0	0
T52	1157	1072	0	0
T53	3215	3138	0	0
T54	4119	4063	0	0
T55	960	868	0	0
T56	1113	1063	0	0
T57	1391	1333	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415038073	414194840	0	0
T16	1214	1120	0	0
T48	68404	63939	0	0
T49	2932	2840	0	0
T51	1034	971	0	0
T52	1157	1072	0	0
T53	3215	3138	0	0
T54	4119	4063	0	0
T55	960	868	0	0
T56	1113	1063	0	0
T57	1391	1333	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1259	1259	0	0
T16	1	1	0	0
T48	1	1	0	0
T49	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	415038073	2933777	0	0
DepthKnown_A	415038073	414194840	0	0
RvalidKnown_A	415038073	414194840	0	0
WreadyKnown_A	415038073	414194840	0	0
gen_passthru_fifo.paramCheckPass	1259	1259	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415038073	2933777	0	0
T49	2932	161	0	0
T51	1034	0	0	0
T52	1157	0	0	0
T53	3215	123	0	0
T54	4119	91	0	0
T55	960	0	0	0
T56	1113	0	0	0
T57	1391	0	0	0
T137	752	0	0	0
T138	3089	134	0	0
T139	0	265	0	0
T140	0	84	0	0
T141	0	115	0	0
T142	0	99	0	0
T143	0	11	0	0
T144	0	319	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415038073	414194840	0	0
T16	1214	1120	0	0
T48	68404	63939	0	0
T49	2932	2840	0	0
T51	1034	971	0	0
T52	1157	1072	0	0
T53	3215	3138	0	0
T54	4119	4063	0	0
T55	960	868	0	0
T56	1113	1063	0	0
T57	1391	1333	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415038073	414194840	0	0
T16	1214	1120	0	0
T48	68404	63939	0	0
T49	2932	2840	0	0
T51	1034	971	0	0
T52	1157	1072	0	0
T53	3215	3138	0	0
T54	4119	4063	0	0
T55	960	868	0	0
T56	1113	1063	0	0
T57	1391	1333	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415038073	414194840	0	0
T16	1214	1120	0	0
T48	68404	63939	0	0
T49	2932	2840	0	0
T51	1034	971	0	0
T52	1157	1072	0	0
T53	3215	3138	0	0
T54	4119	4063	0	0
T55	960	868	0	0
T56	1113	1063	0	0
T57	1391	1333	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1259	1259	0	0
T16	1	1	0	0
T48	1	1	0	0
T49	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0