dashboard | hierarchy | modlist | groups | tests | asserts

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 80.77 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.55 100.00 82.76 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.42 100.00 89.68 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.79 100.00 78.26 88.89 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.90 100.00 78.26 93.33 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.42 100.00 89.68 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00

Go back
Module Instances:
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage
Line No.TotalCoveredPercent
TOTAL2222100.00
ALWAYS7044100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN16211100.00
ALWAYS16522100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN18011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
92 1 1
93 1 1
98 1 1
99 1 1
100 1 1
145 1 1
146 1 1
162 1 1
165 1 1
166 1 1
MISSING_ELSE
175 1 1
176 1 1
180 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage
TotalCoveredPercent
Conditions262180.77
Logical262180.77
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT17,T18

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0CoveredT1,T2,T10
1CoveredT1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0CoveredT1,T2,T10
1CoveredT1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T10

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T10
110Not Covered
111CoveredT1,T2,T10

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT17,T18
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T10

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT17,T18

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T10
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage
Line No.TotalCoveredPercent
Branches 10 10 100.00
TERNARY 88 3 3 100.00
TERNARY 180 2 2 100.00
IF 70 3 3 100.00
IF 157 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 88 (gen_normal_fifo.full) ? -2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T17,T18
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T10


LineNo. Expression -1-: 180 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T10


LineNo. Expression -1-: 70 if ((!rst_ni)) -2-: 72 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 157 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T10
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 412353993 12473642 0 0
DepthKnown_A 412353993 411593036 0 0
RvalidKnown_A 412353993 411593036 0 0
WreadyKnown_A 412353993 411593036 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 412353993 12473642 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412353993 12473642 0 0
T1 335387 25575 0 0
T2 400434 262144 0 0
T3 3393 0 0 0
T4 48538 0 0 0
T5 72914 726 0 0
T6 1053 0 0 0
T8 45438 10772 0 0
T9 0 78 0 0
T10 14232 256 0 0
T20 1100 0 0 0
T21 944 0 0 0
T24 0 23712 0 0
T44 0 25072 0 0
T45 0 22633 0 0
T84 0 262144 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412353993 411593036 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412353993 411593036 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412353993 411593036 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 412353993 12473642 0 0
T1 335387 25575 0 0
T2 400434 262144 0 0
T3 3393 0 0 0
T4 48538 0 0 0
T5 72914 726 0 0
T6 1053 0 0 0
T8 45438 10772 0 0
T9 0 78 0 0
T10 14232 256 0 0
T20 1100 0 0 0
T21 944 0 0 0
T24 0 23712 0 0
T44 0 25072 0 0
T45 0 22633 0 0
T84 0 262144 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage
Line No.TotalCoveredPercent
TOTAL2020100.00
ALWAYS7044100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9200
CONT_ASSIGN9311100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN16211100.00
ALWAYS16511100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN18011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
92 unreachable
93 1 1
98 1 1
99 1 1
100 1 1
145 1 1
146 1 1
162 1 1
165 1 1
166 unreachable
MISSING_ELSE
175 1 1
176 1 1
180 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage
TotalCoveredPercent
Conditions231878.26
Logical231878.26
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0CoveredT1,T2,T10
1CoveredT1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0CoveredT1,T2,T10
1CoveredT1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111UnreachableT1,T2,T10

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T8,T9
101CoveredT1,T2,T10
110Not Covered
111CoveredT1,T2,T10

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T10

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T10
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage
Line No.TotalCoveredPercent
Branches 9 8 88.89
TERNARY 88 3 2 66.67
TERNARY 180 2 2 100.00
IF 70 3 3 100.00
IF 157 1 1 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 88 (gen_normal_fifo.full) ? -2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T10


LineNo. Expression -1-: 180 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T10


LineNo. Expression -1-: 70 if ((!rst_ni)) -2-: 72 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 157 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Unreachable T1,T2,T10
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 412561653 11361072 0 0
DepthKnown_A 412561653 411800696 0 0
RvalidKnown_A 412561653 411800696 0 0
WreadyKnown_A 412561653 411800696 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 412561653 11361072 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 11361072 0 0
T1 335387 8238 0 0
T2 400434 262144 0 0
T3 3393 0 0 0
T4 48538 0 0 0
T5 72914 726 0 0
T6 1053 0 0 0
T8 45438 0 0 0
T10 14232 256 0 0
T20 1100 0 0 0
T21 944 0 0 0
T24 0 23712 0 0
T39 0 119 0 0
T44 0 25072 0 0
T46 0 84673 0 0
T47 0 87372 0 0
T84 0 262144 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 11361072 0 0
T1 335387 8238 0 0
T2 400434 262144 0 0
T3 3393 0 0 0
T4 48538 0 0 0
T5 72914 726 0 0
T6 1053 0 0 0
T8 45438 0 0 0
T10 14232 256 0 0
T20 1100 0 0 0
T21 944 0 0 0
T24 0 23712 0 0
T39 0 119 0 0
T44 0 25072 0 0
T46 0 84673 0 0
T47 0 87372 0 0
T84 0 262144 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%