Group : tl_agent_pkg::pending_req_on_rst_cg
dashboard | hierarchy | modlist | groups | tests | asserts


Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::m_pending_req_on_rst_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::m_pending_req_on_rst_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::m_pending_req_on_rst_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_pending 2 0 2 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_flash_ctrl_eflash_reg_block.cov::m_pending_req_on_rst_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_flash_ctrl_eflash_reg_block.cov::m_pending_req_on_rst_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_flash_ctrl_eflash_reg_block.cov::m_pending_req_on_rst_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_pending 2 0 2 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_flash_ctrl_prim_reg_block.cov::m_pending_req_on_rst_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_flash_ctrl_prim_reg_block.cov::m_pending_req_on_rst_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_flash_ctrl_prim_reg_block.cov::m_pending_req_on_rst_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_pending 2 0 2 100.00 100 1 1 0


Summary for Variable cp_req_pending

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_req_pending

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 9588 1 T12 2 T60 60 T145 1
values[0x1] 36 1 T61 2 T62 2 T145 1


Summary for Variable cp_req_pending

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_req_pending

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 9600 1 T12 2 T60 60 T62 1
values[0x1] 24 1 T61 2 T62 1 T146 1


Summary for Variable cp_req_pending

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_req_pending

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 9608 1 T12 2 T60 60 T61 2
values[0x1] 16 1 T62 1 T145 1 T146 1

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