Group : cip_base_pkg::tl_errors_cg_wrap::tl_errors_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::tl_errors_cg_wrap::tl_errors_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 92.59 1 100 1 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_errors_cgs_wrap[flash_ctrl_eflash_reg_block] 77.78 1 100 1 64 64
tl_errors_cgs_wrap[flash_ctrl_core_reg_block] 100.00 1 100 1 64 64
tl_errors_cgs_wrap[flash_ctrl_prim_reg_block] 100.00 1 100 1 64 64




Group Instance : tl_errors_cgs_wrap[flash_ctrl_eflash_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
77.78 1 100 1 64 64




Summary for Group Instance tl_errors_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 15 5 10 77.78


Variables for Group Instance tl_errors_cgs_wrap[flash_ctrl_eflash_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_csr_size_err 2 1 1 50.00 100 0 0 2
cp_instr_type_err 2 0 2 100.00 100 1 1 2
cp_mem_byte_access_err 2 1 1 50.00 100 1 1 2
cp_mem_ro_err 2 0 2 100.00 100 1 1 2
cp_mem_wo_err 2 1 1 50.00 100 0 0 2
cp_tl_protocol_err 1 0 1 100.00 100 1 1 0
cp_unmapped_err 2 1 1 50.00 100 0 0 2
cp_write_w_instr_type_err 2 1 1 50.00 100 1 1 2



Group Instance : tl_errors_cgs_wrap[flash_ctrl_core_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_errors_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 15 0 15 100.00


Variables for Group Instance tl_errors_cgs_wrap[flash_ctrl_core_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_csr_size_err 2 0 2 100.00 100 1 1 2
cp_instr_type_err 2 0 2 100.00 100 1 1 2
cp_mem_byte_access_err 2 0 2 100.00 100 1 1 2
cp_mem_ro_err 2 0 2 100.00 100 1 1 2
cp_mem_wo_err 2 0 2 100.00 100 1 1 2
cp_tl_protocol_err 1 0 1 100.00 100 1 1 0
cp_unmapped_err 2 0 2 100.00 100 1 1 2
cp_write_w_instr_type_err 2 0 2 100.00 100 1 1 2



Group Instance : tl_errors_cgs_wrap[flash_ctrl_prim_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_errors_cgs_wrap[flash_ctrl_prim_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 15 3 12 100.00


Variables for Group Instance tl_errors_cgs_wrap[flash_ctrl_prim_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_csr_size_err 2 0 2 100.00 100 1 1 2
cp_instr_type_err 2 0 2 100.00 100 1 1 2
cp_mem_byte_access_err 2 1 1 50.00 100 0 0 2
cp_mem_ro_err 2 1 1 50.00 100 0 0 2
cp_mem_wo_err 2 1 1 50.00 100 0 0 2
cp_tl_protocol_err 1 0 1 100.00 100 1 1 0
cp_unmapped_err 2 0 2 100.00 100 1 1 2
cp_write_w_instr_type_err 2 0 2 100.00 100 1 1 2


Summary for Variable cp_csr_size_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_csr_size_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
[auto[1]] 0 0 - - - - - -
auto[0] 1649 0 T63 35 T60 6 T67 25



Summary for Variable cp_instr_type_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_instr_type_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1327 1 T63 35 T60 6 T67 25
auto[1] 322 1 T41 38 T42 27 T43 49



Summary for Variable cp_mem_byte_access_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_mem_byte_access_err

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1649 1 T63 35 T60 6 T67 25



Summary for Variable cp_mem_ro_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_mem_ro_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1644 1 T63 34 T60 6 T67 25
auto[1] 5 1 T63 1 T61 1 T249 1



Summary for Variable cp_mem_wo_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_mem_wo_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
[auto[1]] 0 0 - - - - - -
auto[0] 1649 0 T63 35 T60 6 T67 25



Summary for Variable cp_tl_protocol_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_tl_protocol_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
covered 1226 1 T63 34 T67 25 T61 48



Summary for Variable cp_unmapped_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_unmapped_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
[auto[1]] 0 0 - - - - - -
auto[0] 1649 0 T63 35 T60 6 T67 25



Summary for Variable cp_write_w_instr_type_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_write_w_instr_type_err

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1649 1 T63 35 T60 6 T67 25


Summary for Variable cp_csr_size_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_csr_size_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4840 1 T63 311 T60 2 T67 54
auto[1] 1256 1 T63 111 T67 47 T144 199



Summary for Variable cp_instr_type_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_instr_type_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4780 1 T63 327 T60 2 T67 101
auto[1] 1316 1 T63 95 T61 4 T144 74



Summary for Variable cp_mem_byte_access_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_mem_byte_access_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 5872 1 T63 408 T60 2 T67 92
auto[1] 224 1 T63 14 T67 9 T62 3



Summary for Variable cp_mem_ro_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_mem_ro_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6094 1 T63 422 T60 2 T67 101
auto[1] 2 1 T249 1 T253 1 - -



Summary for Variable cp_mem_wo_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_mem_wo_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 5837 1 T63 402 T60 2 T67 89
auto[1] 259 1 T63 20 T67 12 T144 6



Summary for Variable cp_tl_protocol_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_tl_protocol_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
covered 1550 1 T63 94 T67 29 T144 166



Summary for Variable cp_unmapped_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_unmapped_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6006 1 T63 419 T60 2 T67 97
auto[1] 90 1 T63 3 T67 4 T144 8



Summary for Variable cp_write_w_instr_type_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write_w_instr_type_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4775 1 T63 337 T60 2 T67 101
auto[1] 1321 1 T63 85 T61 5 T144 72


Summary for Variable cp_csr_size_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_csr_size_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6914 1 T63 460 T60 3 T67 117
auto[1] 509 1 T63 32 T67 7 T61 11



Summary for Variable cp_instr_type_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_instr_type_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 5273 1 T63 355 T60 3 T67 120
auto[1] 2150 1 T63 137 T67 4 T61 18



Summary for Variable cp_mem_byte_access_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_mem_byte_access_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
[auto[1]] 0 0 - - - - - -
auto[0] 7423 0 T63 492 T60 3 T67 124



Summary for Variable cp_mem_ro_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_mem_ro_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
[auto[1]] 0 0 - - - - - -
auto[0] 7423 0 T63 492 T60 3 T67 124



Summary for Variable cp_mem_wo_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_mem_wo_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
[auto[1]] 0 0 - - - - - -
auto[0] 7423 0 T63 492 T60 3 T67 124



Summary for Variable cp_tl_protocol_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_tl_protocol_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
covered 2408 1 T63 174 T67 94 T61 34



Summary for Variable cp_unmapped_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_unmapped_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7202 1 T63 470 T60 3 T67 114
auto[1] 221 1 T63 22 T67 10 T61 6



Summary for Variable cp_write_w_instr_type_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write_w_instr_type_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 5361 1 T63 365 T60 3 T67 115
auto[1] 2062 1 T63 127 T67 9 T61 11

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%