SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[flash_ctrl_core_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[flash_ctrl_eflash_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[flash_ctrl_prim_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 18485878 | 1 | T12 | 589 | T22 | 1147 | T23 | 124 | |||
auto[1] | 3853564 | 1 | T63 | 475 | T60 | 5 | T67 | 248 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 22339220 | 1 | T12 | 589 | T22 | 1147 | T23 | 124 | |||
values[1] | 15 | 1 | T233 | 2 | T254 | 1 | T252 | 3 | |||
values[2] | 4 | 1 | T254 | 1 | T252 | 1 | T314 | 1 | |||
values[3] | 110 | 1 | T60 | 4 | T233 | 11 | T234 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 22339239 | 1 | T12 | 589 | T22 | 1147 | T23 | 124 | |||
values[1] | 18 | 1 | T233 | 2 | T245 | 1 | T254 | 1 | |||
values[2] | 7 | 1 | T245 | 1 | T254 | 1 | T252 | 1 | |||
values[3] | 104 | 1 | T60 | 11 | T233 | 9 | T234 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 22339142 | 1 | T12 | 589 | T22 | 1147 | T23 | 124 | |||
auto[TlIntgErrCmd] | 97 | 1 | T60 | 7 | T233 | 5 | T234 | 2 | |||
auto[TlIntgErrData] | 78 | 1 | T60 | 3 | T233 | 1 | T234 | 5 | |||
auto[TlIntgErrBoth] | 125 | 1 | T60 | 10 | T233 | 14 | T234 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[0]] | 0 | 0 | - | - | - | - | - | - | |||
auto[1] | 3442901 | 0 | T63 | 1224 | T60 | 20 | T67 | 838 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 3442713 | 1 | T63 | 1224 | T60 | 8 | T67 | 838 | |||
values[1] | 18 | 1 | T234 | 1 | T254 | 1 | T252 | 3 | |||
values[2] | 6 | 1 | T252 | 1 | T255 | 1 | T336 | 1 | |||
values[3] | 99 | 1 | T60 | 6 | T233 | 9 | T234 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 3442714 | 1 | T63 | 1224 | T60 | 8 | T67 | 838 | |||
values[1] | 15 | 1 | T60 | 1 | T245 | 1 | T254 | 3 | |||
values[2] | 3 | 1 | T233 | 1 | T234 | 1 | T337 | 1 | |||
values[3] | 90 | 1 | T60 | 9 | T233 | 9 | T234 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 3442617 | 1 | T63 | 1224 | T67 | 838 | T61 | 662 | |||
auto[TlIntgErrCmd] | 97 | 1 | T60 | 8 | T233 | 8 | T234 | 3 | |||
auto[TlIntgErrData] | 96 | 1 | T60 | 8 | T233 | 6 | T234 | 4 | |||
auto[TlIntgErrBoth] | 91 | 1 | T60 | 4 | T233 | 6 | T234 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 78743 | 0 | T12 | 84 | T63 | 1565 | T60 | 1261 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 78541 | 1 | T12 | 84 | T63 | 1565 | T60 | 1247 | |||
values[1] | 16 | 1 | T60 | 6 | T234 | 1 | T252 | 1 | |||
values[2] | 4 | 1 | T254 | 1 | T252 | 2 | T338 | 1 | |||
values[3] | 114 | 1 | T60 | 6 | T233 | 6 | T234 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 78545 | 1 | T12 | 84 | T63 | 1565 | T60 | 1247 | |||
values[1] | 16 | 1 | T60 | 4 | T233 | 1 | T245 | 2 | |||
values[2] | 6 | 1 | T60 | 1 | T233 | 1 | T339 | 1 | |||
values[3] | 90 | 1 | T60 | 5 | T233 | 5 | T245 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 78443 | 1 | T12 | 84 | T63 | 1565 | T60 | 1241 | |||
auto[TlIntgErrCmd] | 102 | 1 | T60 | 6 | T233 | 5 | T234 | 6 | |||
auto[TlIntgErrData] | 98 | 1 | T60 | 6 | T233 | 11 | T234 | 3 | |||
auto[TlIntgErrBoth] | 100 | 1 | T60 | 8 | T233 | 4 | T234 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |