Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	16559129	1		T12	344		T22	21		T23	75
full_word	5780313	1		T12	245		T22	1126		T23	49

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	22339142	1		T12	589		T22	1147		T23	124
auto[TlIntgErrCmd]	97	1		T60	7		T233	5		T234	2
auto[TlIntgErrData]	78	1		T60	3		T233	1		T234	5
auto[TlIntgErrBoth]	125	1		T60	10		T233	14		T234	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	19106971	1		T12	381		T22	579		T23	68
auto[1]	3232471	1		T12	208		T22	568		T23	56

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	16070792	1		T12	266		T22	21		T23	62
auto[TlIntgErrNone]	partial	auto[1]	488065	1		T12	78		T23	13		T63	1063
auto[TlIntgErrNone]	full_word	auto[0]	3036041	1		T12	115		T22	558		T23	6
auto[TlIntgErrNone]	full_word	auto[1]	2744244	1		T12	130		T22	568		T23	43
auto[TlIntgErrCmd]	partial	auto[0]	37	1		T60	4		T233	2		T245	2
auto[TlIntgErrCmd]	partial	auto[1]	49	1		T60	3		T233	3		T234	1
auto[TlIntgErrCmd]	full_word	auto[0]	6	1		T234	1		T254	1		T340	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T255	1		T339	1		T248	1
auto[TlIntgErrData]	partial	auto[0]	32	1		T60	1		T233	1		T234	2
auto[TlIntgErrData]	partial	auto[1]	39	1		T60	1		T234	3		T245	2
auto[TlIntgErrData]	full_word	auto[0]	2	1		T254	1		T248	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1		T60	1		T339	1		T336	1
auto[TlIntgErrBoth]	partial	auto[0]	56	1		T60	4		T233	5		T234	2
auto[TlIntgErrBoth]	partial	auto[1]	59	1		T60	6		T233	8		T245	4
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T234	1		T255	1		T314	2
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T233	1		T340	1		T341	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	18993	1		T63	771		T60	19		T67	542
full_word	3423908	1		T63	453		T60	1		T67	296

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3442617	1		T63	1224		T67	838		T61	662
auto[TlIntgErrCmd]	97	1		T60	8		T233	8		T234	3
auto[TlIntgErrData]	96	1		T60	8		T233	6		T234	4
auto[TlIntgErrBoth]	91	1		T60	4		T233	6		T234	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3418954	1		T63	34		T60	7		T67	25
auto[1]	23947	1		T63	1190		T60	13		T67	813

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1076	1		T63	29		T67	24		T61	44
auto[TlIntgErrNone]	partial	auto[1]	17649	1		T63	742		T67	518		T61	436
auto[TlIntgErrNone]	full_word	auto[0]	3417771	1		T63	5		T67	1		T61	4
auto[TlIntgErrNone]	full_word	auto[1]	6121	1		T63	448		T67	295		T61	178
auto[TlIntgErrCmd]	partial	auto[0]	30	1		T60	4		T233	3		T234	2
auto[TlIntgErrCmd]	partial	auto[1]	64	1		T60	4		T233	4		T234	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T233	1		T342	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	1	1		T245	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	43	1		T60	3		T233	2		T234	2
auto[TlIntgErrData]	partial	auto[1]	45	1		T60	5		T233	4		T234	2
auto[TlIntgErrData]	full_word	auto[0]	4	1		T254	1		T255	1		T248	1
auto[TlIntgErrData]	full_word	auto[1]	4	1		T245	1		T341	1		T336	1
auto[TlIntgErrBoth]	partial	auto[0]	25	1		T233	4		T245	1		T254	3
auto[TlIntgErrBoth]	partial	auto[1]	61	1		T60	3		T233	2		T234	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T254	1		T340	1		T343	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1		T60	1		T341	1		-	-