Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 100.00 86.36 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 100.00 86.36 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.36 100.00 89.45 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 100.00 86.36 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 100.00 86.36 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.36 100.00 89.45 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : flash_phy_rd_buf_dep
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS4877100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7111100.00
CONT_ASSIGN7211100.00
ALWAYS7666100.00
ALWAYS9033100.00
CONT_ASSIGN9711100.00
ALWAYS11600
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
MISSING_ELSE
54 1 1
55 1 1
MISSING_ELSE
61 1 1
62 1 1
65 1 1
66 1 1
71 1 1
72 1 1
76 1 1
77 1 1
79 1 1
80 1 1
MISSING_ELSE
82 1 1
83 1 1
MISSING_ELSE
90 1 1
91 1 1
92 1 1
97 1 1
116 unreachable
117 unreachable
118 unreachable


Cond Coverage for Module : flash_phy_rd_buf_dep
TotalCoveredPercent
Conditions221986.36
Logical221986.36
Non-Logical00
Event00

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T3,T4

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T3,T4
110Not Covered
111CoveredT1,T3,T4

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T44,T117
11CoveredT1,T3,T4

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---
-1--2-StatusTests
01CoveredT1,T44,T117
10CoveredT1,T2,T3
11CoveredT1,T3,T4

Branch Coverage for Module : flash_phy_rd_buf_dep
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 71 2 2 100.00
TERNARY 72 2 2 100.00
IF 51 2 2 100.00
IF 54 2 2 100.00
IF 76 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 ((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T3,T4


LineNo. Expression -1-: 72 ((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T3,T4


LineNo. Expression -1-: 51 if (wr_buf_i[i])

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 54 if (rd_buf_i[i])

Branches:
-1-StatusTests
1 Covered T1,T3,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 76 if ((!rst_ni)) -2-: 79 if (fin_cnt_incr) -3-: 82 if (fin_cnt_decr)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T3,T6
0 0 - Covered T1,T2,T3
0 - 1 Covered T1,T3,T6
0 - 0 Covered T1,T2,T3


Assert Coverage for Module : flash_phy_rd_buf_dep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BufferDecrUnderRun_A 654167136 5523843 0 0
BufferDepRsp_A 654167136 652737450 0 0
BufferIncrOverFlow_A 654167136 5523851 0 0
DepBufferRspOrder_A 654167137 14318257 0 0


BufferDecrUnderRun_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 654167136 5523843 0 0
T1 9195 257 0 0
T2 3842 0 0 0
T3 327480 2432 0 0
T4 634036 47124 0 0
T5 350036 1024 0 0
T6 262738 0 0 0
T7 0 32079 0 0
T8 0 31101 0 0
T11 8102 0 0 0
T15 8942 0 0 0
T16 1992 0 0 0
T17 91054 0 0 0
T18 0 1 0 0
T19 4161 78 0 0
T20 0 23508 0 0
T40 0 4928 0 0
T44 0 58 0 0
T46 1505 0 0 0
T48 0 2712 0 0
T49 0 101 0 0
T50 0 239 0 0
T51 0 241 0 0
T71 0 14699 0 0

BufferDepRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 654167136 652737450 0 0
T1 18390 18076 0 0
T2 7684 6384 0 0
T3 327480 327324 0 0
T4 634036 633894 0 0
T5 350036 349908 0 0
T6 262738 212350 0 0
T11 8102 6698 0 0
T15 8942 8752 0 0
T16 1992 1824 0 0
T17 91054 90712 0 0

BufferIncrOverFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 654167136 5523851 0 0
T1 9195 257 0 0
T2 3842 0 0 0
T3 327480 2432 0 0
T4 634036 47124 0 0
T5 350036 1024 0 0
T6 262738 0 0 0
T7 0 32079 0 0
T8 0 31101 0 0
T11 8102 0 0 0
T15 8942 0 0 0
T16 1992 0 0 0
T17 91054 0 0 0
T18 0 1 0 0
T19 4161 78 0 0
T20 0 23508 0 0
T40 0 4928 0 0
T44 0 58 0 0
T46 1505 0 0 0
T48 0 2712 0 0
T49 0 101 0 0
T50 0 239 0 0
T51 0 241 0 0
T71 0 14699 0 0

DepBufferRspOrder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 654167137 14318257 0 0
T1 9195 321 0 0
T2 3842 164 0 0
T3 327480 2464 0 0
T4 634036 47156 0 0
T5 350036 1056 0 0
T6 262738 0 0 0
T7 0 13904 0 0
T8 0 15783 0 0
T11 8102 228 0 0
T15 8942 32 0 0
T16 1992 32 0 0
T17 91054 64 0 0
T18 0 1 0 0
T19 4161 142 0 0
T20 0 23508 0 0
T44 0 58 0 0
T46 1505 0 0 0
T51 0 241 0 0
T71 0 14699 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS4877100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7111100.00
CONT_ASSIGN7211100.00
ALWAYS7666100.00
ALWAYS9033100.00
CONT_ASSIGN9711100.00
ALWAYS11600
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
MISSING_ELSE
54 1 1
55 1 1
MISSING_ELSE
61 1 1
62 1 1
65 1 1
66 1 1
71 1 1
72 1 1
76 1 1
77 1 1
79 1 1
80 1 1
MISSING_ELSE
82 1 1
83 1 1
MISSING_ELSE
90 1 1
91 1 1
92 1 1
97 1 1
116 unreachable
117 unreachable
118 unreachable


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
TotalCoveredPercent
Conditions221986.36
Logical221986.36
Non-Logical00
Event00

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T3,T4

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T3,T4
110Not Covered
111CoveredT1,T3,T4

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T117,T141
11CoveredT1,T3,T4

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---
-1--2-StatusTests
01CoveredT1,T117,T141
10CoveredT1,T2,T3
11CoveredT1,T3,T4

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 71 2 2 100.00
TERNARY 72 2 2 100.00
IF 51 2 2 100.00
IF 54 2 2 100.00
IF 76 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 ((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T3,T4


LineNo. Expression -1-: 72 ((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T3,T4


LineNo. Expression -1-: 51 if (wr_buf_i[i])

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 54 if (rd_buf_i[i])

Branches:
-1-StatusTests
1 Covered T1,T3,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 76 if ((!rst_ni)) -2-: 79 if (fin_cnt_incr) -3-: 82 if (fin_cnt_decr)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T3,T6
0 0 - Covered T1,T2,T3
0 - 1 Covered T1,T3,T6
0 - 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BufferDecrUnderRun_A 327083568 3212905 0 0
BufferDepRsp_A 327083568 326368725 0 0
BufferIncrOverFlow_A 327083568 3212910 0 0
DepBufferRspOrder_A 327083568 7882132 0 0


BufferDecrUnderRun_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083568 3212905 0 0
T1 9195 257 0 0
T2 3842 0 0 0
T3 163740 1160 0 0
T4 317018 23917 0 0
T5 175018 1024 0 0
T6 131369 0 0 0
T7 0 18175 0 0
T8 0 15318 0 0
T11 4051 0 0 0
T15 4471 0 0 0
T16 996 0 0 0
T17 45527 0 0 0
T40 0 4928 0 0
T48 0 2712 0 0
T49 0 101 0 0
T50 0 239 0 0

BufferDepRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083568 326368725 0 0
T1 9195 9038 0 0
T2 3842 3192 0 0
T3 163740 163662 0 0
T4 317018 316947 0 0
T5 175018 174954 0 0
T6 131369 106175 0 0
T11 4051 3349 0 0
T15 4471 4376 0 0
T16 996 912 0 0
T17 45527 45356 0 0

BufferIncrOverFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083568 3212910 0 0
T1 9195 257 0 0
T2 3842 0 0 0
T3 163740 1160 0 0
T4 317018 23917 0 0
T5 175018 1024 0 0
T6 131369 0 0 0
T7 0 18175 0 0
T8 0 15318 0 0
T11 4051 0 0 0
T15 4471 0 0 0
T16 996 0 0 0
T17 45527 0 0 0
T40 0 4928 0 0
T48 0 2712 0 0
T49 0 101 0 0
T50 0 239 0 0

DepBufferRspOrder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083568 7882132 0 0
T1 9195 321 0 0
T2 3842 164 0 0
T3 163740 1192 0 0
T4 317018 23949 0 0
T5 175018 1056 0 0
T6 131369 0 0 0
T11 4051 228 0 0
T15 4471 32 0 0
T16 996 32 0 0
T17 45527 64 0 0
T19 0 64 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS4877100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7111100.00
CONT_ASSIGN7211100.00
ALWAYS7666100.00
ALWAYS9033100.00
CONT_ASSIGN9711100.00
ALWAYS11600
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
MISSING_ELSE
54 1 1
55 1 1
MISSING_ELSE
61 1 1
62 1 1
65 1 1
66 1 1
71 1 1
72 1 1
76 1 1
77 1 1
79 1 1
80 1 1
MISSING_ELSE
82 1 1
83 1 1
MISSING_ELSE
90 1 1
91 1 1
92 1 1
97 1 1
116 unreachable
117 unreachable
118 unreachable


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
TotalCoveredPercent
Conditions221986.36
Logical221986.36
Non-Logical00
Event00

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------
-1--2--3-StatusTests
011CoveredT59,T152,T173
101CoveredT1,T2,T3
110Not Covered
111CoveredT3,T4,T19

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT3,T4,T19
110Not Covered
111CoveredT3,T4,T19

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------
-1-StatusTests
0CoveredT3,T4,T19
1CoveredT1,T2,T3

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT44,T52,T163
11CoveredT3,T4,T19

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------
-1-StatusTests
0CoveredT3,T4,T19
1CoveredT1,T2,T3

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---
-1--2-StatusTests
01CoveredT44,T52,T163
10CoveredT1,T2,T3
11CoveredT3,T4,T19

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 71 2 2 100.00
TERNARY 72 2 2 100.00
IF 51 2 2 100.00
IF 54 2 2 100.00
IF 76 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 ((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T3,T4,T19


LineNo. Expression -1-: 72 ((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T3,T4,T19


LineNo. Expression -1-: 51 if (wr_buf_i[i])

Branches:
-1-StatusTests
1 Covered T3,T4,T19
0 Covered T1,T2,T3


LineNo. Expression -1-: 54 if (rd_buf_i[i])

Branches:
-1-StatusTests
1 Covered T3,T6,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 76 if ((!rst_ni)) -2-: 79 if (fin_cnt_incr) -3-: 82 if (fin_cnt_decr)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T3,T6,T4
0 0 - Covered T1,T2,T3
0 - 1 Covered T3,T6,T4
0 - 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BufferDecrUnderRun_A 327083568 2310938 0 0
BufferDepRsp_A 327083568 326368725 0 0
BufferIncrOverFlow_A 327083568 2310941 0 0
DepBufferRspOrder_A 327083569 6436125 0 0


BufferDecrUnderRun_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083568 2310938 0 0
T3 163740 1272 0 0
T4 317018 23207 0 0
T5 175018 0 0 0
T6 131369 0 0 0
T7 0 13904 0 0
T8 0 15783 0 0
T11 4051 0 0 0
T15 4471 0 0 0
T16 996 0 0 0
T17 45527 0 0 0
T18 0 1 0 0
T19 4161 78 0 0
T20 0 23508 0 0
T44 0 58 0 0
T46 1505 0 0 0
T51 0 241 0 0
T71 0 14699 0 0

BufferDepRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083568 326368725 0 0
T1 9195 9038 0 0
T2 3842 3192 0 0
T3 163740 163662 0 0
T4 317018 316947 0 0
T5 175018 174954 0 0
T6 131369 106175 0 0
T11 4051 3349 0 0
T15 4471 4376 0 0
T16 996 912 0 0
T17 45527 45356 0 0

BufferIncrOverFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083568 2310941 0 0
T3 163740 1272 0 0
T4 317018 23207 0 0
T5 175018 0 0 0
T6 131369 0 0 0
T7 0 13904 0 0
T8 0 15783 0 0
T11 4051 0 0 0
T15 4471 0 0 0
T16 996 0 0 0
T17 45527 0 0 0
T18 0 1 0 0
T19 4161 78 0 0
T20 0 23508 0 0
T44 0 58 0 0
T46 1505 0 0 0
T51 0 241 0 0
T71 0 14699 0 0

DepBufferRspOrder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083569 6436125 0 0
T3 163740 1272 0 0
T4 317018 23207 0 0
T5 175018 0 0 0
T6 131369 0 0 0
T7 0 13904 0 0
T8 0 15783 0 0
T11 4051 0 0 0
T15 4471 0 0 0
T16 996 0 0 0
T17 45527 0 0 0
T18 0 1 0 0
T19 4161 78 0 0
T20 0 23508 0 0
T44 0 58 0 0
T46 1505 0 0 0
T51 0 241 0 0
T71 0 14699 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%