Unified Coverage Report :: Module :: flash_phy_core

Module : flash_phy_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.49	97.47	91.51		100.00	93.48	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[1].u_core	94.29	96.20	83.96		100.00	91.30	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core	96.49	97.47	91.51		100.00	93.48	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.29	96.20	83.96		100.00	91.30	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.29	97.65	92.24	98.97	100.00	96.91	97.98

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.26	97.67	85.11			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prog_data.u_prog	97.50	100.00	93.65	95.00	100.00	96.36	100.00
u_disable_buf	100.00	100.00					100.00
u_erase	92.22	100.00	88.89		100.00	80.00
u_host_arb	91.95	75.93	91.89			100.00	100.00
u_host_outstanding_cnt	100.00			100.00
u_rd	97.53	99.15	93.05	100.00		99.25	96.23
u_scramble	98.18	100.00	90.91	100.00		100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.49	97.47	91.51		100.00	93.48	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.67	97.77	93.02	100.00	100.00	97.25	97.98

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.26	97.67	85.11			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prog_data.u_prog	98.34	100.00	93.65	100.00	100.00	96.36	100.00
u_disable_buf	100.00	100.00					100.00
u_erase	92.22	100.00	88.89		100.00	80.00
u_host_arb	93.98	75.93	100.00			100.00	100.00
u_host_outstanding_cnt	100.00			100.00
u_rd	97.53	99.15	93.05	100.00		99.25	96.23
u_scramble	98.18	100.00	90.91	100.00		100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : flash_phy_core

	Line No.	Total	Covered	Percent
TOTAL		79	77	97.47
ALWAYS	154	6	6	100.00
ALWAYS	167	3	3	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
ALWAYS	206	4	4	100.00
ALWAYS	218	6	5	83.33
ALWAYS	232	6	5	83.33
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	319	1	1	100.00
CONT_ASSIGN	323	1	1	100.00
ALWAYS	327	29	29	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	578	1	1	100.00
CONT_ASSIGN	585	1	1	100.00
CONT_ASSIGN	602	1	1	100.00
CONT_ASSIGN	603	1	1	100.00
CONT_ASSIGN	604	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
154	1	1
155	1	1
156	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
167	3	3
199	1	1
203	1	1
206	1	1
207	1	1
208	1	1
209	1	1
			MISSING_ELSE
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	0	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	0	1
			MISSING_ELSE
279	1	1
282	1	1
283	1	1
284	1	1
289	1	1
319	1	1
323	1	1
327	1	1
328	1	1
329	1	1
330	1	1
331	1	1
333	1	1
335	1	1
336	1	1
337	1	1
338	1	1
339	1	1
340	1	1
341	1	1
342	1	1
343	1	1
			MISSING_ELSE
349	1	1
350	1	1
351	1	1
			MISSING_ELSE
358	1	1
359	1	1
360	1	1
361	1	1
			MISSING_ELSE
367	1	1
368	1	1
369	1	1
370	1	1
371	1	1
			MISSING_ELSE
376	1	1
377	1	1
390	1	1
394	1	1
395	1	1
396	1	1
397	1	1
398	1	1
399	1	1
400	1	1
417	1	1
430	1	1
550	1	1
578	1	1
585	1	1
602	1	1
603	1	1
604	1	1

---

Cond Coverage for Module : flash_phy_core

	Total	Covered	Percent
Conditions	106	97	91.51
Logical	106	97	91.51
Non-Logical	0	0
Event	0	0

 LINE       199
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T19
1	1	Covered	T156,T157

 LINE       199
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       203
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T4
1	1	Not Covered

 LINE       208
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T156,T157

 LINE       220
 EXPRESSION (host_outstanding == '0)
            ------------1-----------

-1-	Status	Tests
0	Covered	T1,T6,T4
1	Covered	T1,T2,T3

 LINE       234
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       234
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T6,T4
1	Covered	T1,T2,T3

 LINE       245
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T4,T7
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T19

 LINE       245
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T7
1	0	1	Covered	T1,T6,T4
1	1	0	Covered	T18,T92,T151
1	1	1	Covered	T1,T4,T19

 LINE       283
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T7,T8
1	1	Covered	T1,T4,T19

 LINE       284
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T4
1	1	Covered	T1,T4,T19

 LINE       319
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T19

 LINE       319
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T158,T159
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T19

 LINE       323
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T7,T8

 LINE       338
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       340
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T17

 LINE       390
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T18,T92,T151
1	0	Covered	T160,T161

 LINE       390
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T160,T161

 LINE       390
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T18,T92,T151

 LINE       390
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       394
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T19

 LINE       395
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T19

 LINE       396
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T19

 LINE       397
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T19

 LINE       398
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       399
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T17

 LINE       400
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

 LINE       400
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T52,T53,T54
1	0	Covered	T1,T2,T3

 LINE       430
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       430
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T4
1	0	Not Covered
1	1	Not Covered

 LINE       430
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T4

 LINE       433
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       433
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T19
1	0	Covered	T1,T2,T3

 LINE       433
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       550
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T17,T19

 LINE       556
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T17,T19

 LINE       556
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T17,T19

 LINE       556
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T17,T19

 LINE       578
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T13,T14
1	0	Covered	T6,T13,T14

---

FSM Coverage for Module : flash_phy_core

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrl	343	Covered	T12
StCtrlProg	341	Covered	T12
StCtrlRead	339	Covered	T12
StDisable	337	Covered	T12
StIdle	351	Covered	T12

transitions	Line No.	Covered	Tests
StCtrl->StIdle	371	Covered	T12
StCtrlProg->StIdle	361	Covered	T12
StCtrlRead->StIdle	351	Covered	T12
StIdle->StCtrl	343	Covered	T12
StIdle->StCtrlProg	341	Covered	T12
StIdle->StCtrlRead	339	Covered	T12
StIdle->StDisable	337	Covered	T12

---

Branch Coverage for Module : flash_phy_core

	Line No.	Total	Covered	Percent
Branches		46	43	93.48
TERNARY	319	2	2	100.00
TERNARY	394	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	396	2	2	100.00
TERNARY	397	2	2	100.00
TERNARY	550	2	2	100.00
TERNARY	433	2	1	50.00
TERNARY	556	2	2	100.00
IF	154	4	4	100.00
IF	167	2	2	100.00
IF	206	3	3	100.00
IF	218	4	3	75.00
IF	232	4	3	75.00
CASE	333	13	13	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	319	((phy_req & host_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	394	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	396	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	397	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	550	(prog_calc_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T17,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	433	(arb_host_gnt_err) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	556	(prog_op_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T17,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	154	if ((!rst_ni))
-2-:	156	if (ctrl_rsp_vld)
-3-:	158	if (inc_arb_cnt)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T4,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	167	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	206	if ((!rst_ni))
-2-:	208	if ((host_gnt_err_event | host_outstanding_err_event))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T156,T157
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	218	if ((!rst_ni))
-2-:	220	if ((host_outstanding == '0))
-3-:	222	if (host_gnt_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Not Covered
0	0	0	Covered	T1,T6,T4

	LineNo.	Expression
-1-:	232	if ((!rst_ni))
-2-:	234	if (((host_outstanding == '0) && ctrl_fsm_idle))
-3-:	236	if (host_outstanding_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	333	case (state_q)
-2-:	336	if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx]))
-3-:	338	if ((ctrl_gnt && rd_i))
-4-:	340	if ((ctrl_gnt && prog_i))
-5-:	342	if (ctrl_gnt)
-6-:	349	if (rd_stage_data_valid)
-7-:	359	if (prog_ack)
-8-:	369	if (erase_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StIdle	1	-	-	-	-	-	-	Covered	T2,T6,T11
StIdle	0	1	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	0	1	-	-	-	-	Covered	T3,T4,T17
StIdle	0	0	0	1	-	-	-	Covered	T1,T2,T3
StIdle	0	0	0	0	-	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	1	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	0	-	-	Covered	T1,T2,T3
StCtrlProg	-	-	-	-	-	1	-	Covered	T3,T4,T17
StCtrlProg	-	-	-	-	-	0	-	Covered	T3,T4,T17
StCtrl	-	-	-	-	-	-	1	Covered	T1,T3,T5
StCtrl	-	-	-	-	-	-	0	Covered	T1,T2,T3
StDisable	-	-	-	-	-	-	-	Covered	T2,T6,T11
default	-	-	-	-	-	-	-	Covered	T6,T13,T14

---

Assert Coverage for Module : flash_phy_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ArbCntMax_A	654167136	3574198	0	0
CtrlPrio_A	654167136	3574197	0	0
HostTransIdleChk_A	654167136	36947120	0	0
NoRemainder_A	1752	1752	0	0
OneHotReqs_A	654167136	652737450	0	0
Pow2Multiple_A	1752	1752	0	0
RdTxnCheck_A	653936324	652506638	0	0
u_state_regs_A	654167136	652737450	0	0

ArbCntMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	654167136	3574198	0	0
T4	634036	15533	0	0
T5	350036	0	0	0
T7	0	3422	0	0
T8	0	89095	0	0
T11	8102	0	0	0
T15	8942	0	0	0
T16	1992	0	0	0
T17	91054	0	0	0
T18	2084	0	0	0
T19	8322	0	0	0
T20	0	18121	0	0
T21	0	6561	0	0
T35	0	1479	0	0
T40	684724	0	0	0
T46	3010	0	0	0
T52	0	84	0	0
T71	0	77250	0	0
T72	0	88683	0	0
T162	0	5436	0	0
T163	0	2740	0	0

CtrlPrio_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	654167136	3574197	0	0
T4	634036	15533	0	0
T5	350036	0	0	0
T7	0	3422	0	0
T8	0	89095	0	0
T11	8102	0	0	0
T15	8942	0	0	0
T16	1992	0	0	0
T17	91054	0	0	0
T18	2084	0	0	0
T19	8322	0	0	0
T20	0	18121	0	0
T21	0	6561	0	0
T35	0	1479	0	0
T40	684724	0	0	0
T46	3010	0	0	0
T52	0	84	0	0
T71	0	77250	0	0
T72	0	88683	0	0
T162	0	5436	0	0
T163	0	2740	0	0

HostTransIdleChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	654167136	36947120	0	0
T1	9195	33	0	0
T2	3842	0	0	0
T3	163740	0	0	0
T4	634036	173843	0	0
T5	350036	0	0	0
T6	262738	92	0	0
T7	0	33418	0	0
T8	0	854149	0	0
T11	8102	0	0	0
T15	8942	0	0	0
T16	1992	0	0	0
T17	91054	0	0	0
T18	0	2	0	0
T19	4161	24	0	0
T20	0	174463	0	0
T21	0	29807	0	0
T40	342362	0	0	0
T44	0	29	0	0
T46	1505	0	0	0
T49	0	16	0	0
T50	0	16	0	0
T51	0	16	0	0
T71	0	839461	0	0

NoRemainder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1752	1752	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T11	2	2	0	0
T15	2	2	0	0
T16	2	2	0	0
T17	2	2	0	0

OneHotReqs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	654167136	652737450	0	0
T1	18390	18076	0	0
T2	7684	6384	0	0
T3	327480	327324	0	0
T4	634036	633894	0	0
T5	350036	349908	0	0
T6	262738	212350	0	0
T11	8102	6698	0	0
T15	8942	8752	0	0
T16	1992	1824	0	0
T17	91054	90712	0	0

Pow2Multiple_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1752	1752	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T11	2	2	0	0
T15	2	2	0	0
T16	2	2	0	0
T17	2	2	0	0

RdTxnCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653936324	652506638	0	0
T1	18390	18076	0	0
T2	7684	6384	0	0
T3	327480	327324	0	0
T4	634036	633894	0	0
T5	350036	349908	0	0
T6	175994	125606	0	0
T11	8102	6698	0	0
T15	8942	8752	0	0
T16	1992	1824	0	0
T17	91054	90712	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	654167136	652737450	0	0
T1	18390	18076	0	0
T2	7684	6384	0	0
T3	327480	327324	0	0
T4	634036	633894	0	0
T5	350036	349908	0	0
T6	262738	212350	0	0
T11	8102	6698	0	0
T15	8942	8752	0	0
T16	1992	1824	0	0
T17	91054	90712	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Line No.	Total	Covered	Percent
TOTAL		79	76	96.20
ALWAYS	154	6	6	100.00
ALWAYS	167	3	3	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
ALWAYS	206	4	3	75.00
ALWAYS	218	6	5	83.33
ALWAYS	232	6	5	83.33
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	319	1	1	100.00
CONT_ASSIGN	323	1	1	100.00
ALWAYS	327	29	29	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	578	1	1	100.00
CONT_ASSIGN	585	1	1	100.00
CONT_ASSIGN	602	1	1	100.00
CONT_ASSIGN	603	1	1	100.00
CONT_ASSIGN	604	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
154	1	1
155	1	1
156	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
167	3	3
199	1	1
203	1	1
206	1	1
207	1	1
208	1	1
209	0	1
			MISSING_ELSE
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	0	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	0	1
			MISSING_ELSE
279	1	1
282	1	1
283	1	1
284	1	1
289	1	1
319	1	1
323	1	1
327	1	1
328	1	1
329	1	1
330	1	1
331	1	1
333	1	1
335	1	1
336	1	1
337	1	1
338	1	1
339	1	1
340	1	1
341	1	1
342	1	1
343	1	1
			MISSING_ELSE
349	1	1
350	1	1
351	1	1
			MISSING_ELSE
358	1	1
359	1	1
360	1	1
361	1	1
			MISSING_ELSE
367	1	1
368	1	1
369	1	1
370	1	1
371	1	1
			MISSING_ELSE
376	1	1
377	1	1
390	1	1
394	1	1
395	1	1
396	1	1
397	1	1
398	1	1
399	1	1
400	1	1
417	1	1
430	1	1
550	1	1
578	1	1
585	1	1
602	1	1
603	1	1
604	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Total	Covered	Percent
Conditions	106	89	83.96
Logical	106	89	83.96
Non-Logical	0	0
Event	0	0

 LINE       199
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T19,T18
1	1	Not Covered

 LINE       199
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       203
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T17
1	0	Covered	T6,T4,T19
1	1	Not Covered

 LINE       208
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       220
 EXPRESSION (host_outstanding == '0)
            ------------1-----------

-1-	Status	Tests
0	Covered	T6,T4,T19
1	Covered	T1,T2,T3

 LINE       234
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T19
1	0	Covered	T3,T4,T17
1	1	Covered	T1,T2,T3

 LINE       234
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T6,T4,T19
1	Covered	T1,T2,T3

 LINE       245
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T7,T8
1	1	0	Not Covered
1	1	1	Covered	T4,T19,T18

 LINE       245
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T7,T8
1	0	1	Covered	T6,T4,T19
1	1	0	Not Covered
1	1	1	Covered	T4,T19,T18

 LINE       283
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T7,T8
1	1	Covered	T4,T19,T18

 LINE       284
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T19
1	0	Covered	T6,T4,T19
1	1	Covered	T4,T19,T18

 LINE       319
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T19,T18

 LINE       319
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T4,T17
1	1	Covered	T4,T19,T18

 LINE       323
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T19,T18
1	0	Covered	T3,T4,T17
1	1	Covered	T4,T7,T8

 LINE       338
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T17
1	1	Covered	T3,T4,T19

 LINE       340
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T17
1	0	Covered	T3,T33,T59
1	1	Covered	T3,T4,T17

 LINE       390
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       390
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T17
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       390
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T19,T18
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       390
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       394
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T19,T18

 LINE       395
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T19,T18

 LINE       396
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T19,T18

 LINE       397
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T19,T18

 LINE       398
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T17
1	1	Covered	T3,T4,T19

 LINE       399
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T17
1	0	Covered	T3,T4,T19
1	1	Covered	T3,T4,T17

 LINE       400
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T17
1	1	Covered	T3,T33,T59

 LINE       400
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T52,T53,T54
1	0	Covered	T1,T2,T3

 LINE       430
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       430
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T19
1	0	Not Covered
1	1	Not Covered

 LINE       430
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T4,T19

 LINE       433
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T17
1	1	Covered	T3,T4,T19

 LINE       433
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T19,T18
1	0	Covered	T1,T2,T3

 LINE       433
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       550
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T19,T44

 LINE       556
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T19,T18
1	0	Covered	T4,T19,T44

 LINE       556
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T19,T7
1	0	Covered	T4,T19,T44

 LINE       556
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T19,T44

 LINE       578
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T13,T14
1	0	Covered	T6,T13,T14

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrl	343	Covered	T12
StCtrlProg	341	Covered	T12
StCtrlRead	339	Covered	T12
StDisable	337	Covered	T12
StIdle	351	Covered	T12

transitions	Line No.	Covered	Tests
StCtrl->StIdle	371	Covered	T12
StCtrlProg->StIdle	361	Covered	T12
StCtrlRead->StIdle	351	Covered	T12
StIdle->StCtrl	343	Covered	T12
StIdle->StCtrlProg	341	Covered	T12
StIdle->StCtrlRead	339	Covered	T12
StIdle->StDisable	337	Covered	T12

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Line No.	Total	Covered	Percent
Branches		46	42	91.30
TERNARY	319	2	2	100.00
TERNARY	394	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	396	2	2	100.00
TERNARY	397	2	2	100.00
TERNARY	550	2	2	100.00
TERNARY	433	2	1	50.00
TERNARY	556	2	2	100.00
IF	154	4	4	100.00
IF	167	2	2	100.00
IF	206	3	2	66.67
IF	218	4	3	75.00
IF	232	4	3	75.00
CASE	333	13	13	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	319	((phy_req & host_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T19,T18
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	394	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T19,T18
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T19,T18
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	396	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T19,T18
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	397	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T19,T18
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	550	(prog_calc_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T19,T44
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	433	(arb_host_gnt_err) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	556	(prog_op_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T19,T44
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	154	if ((!rst_ni))
-2-:	156	if (ctrl_rsp_vld)
-3-:	158	if (inc_arb_cnt)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T17
0	0	1	Covered	T4,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	167	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	206	if ((!rst_ni))
-2-:	208	if ((host_gnt_err_event | host_outstanding_err_event))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	218	if ((!rst_ni))
-2-:	220	if ((host_outstanding == '0))
-3-:	222	if (host_gnt_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Not Covered
0	0	0	Covered	T6,T4,T19

	LineNo.	Expression
-1-:	232	if ((!rst_ni))
-2-:	234	if (((host_outstanding == '0) && ctrl_fsm_idle))
-3-:	236	if (host_outstanding_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Not Covered
0	0	0	Covered	T3,T6,T4

	LineNo.	Expression
-1-:	333	case (state_q)
-2-:	336	if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx]))
-3-:	338	if ((ctrl_gnt && rd_i))
-4-:	340	if ((ctrl_gnt && prog_i))
-5-:	342	if (ctrl_gnt)
-6-:	349	if (rd_stage_data_valid)
-7-:	359	if (prog_ack)
-8-:	369	if (erase_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StIdle	1	-	-	-	-	-	-	Covered	T2,T6,T11
StIdle	0	1	-	-	-	-	-	Covered	T3,T4,T19
StIdle	0	0	1	-	-	-	-	Covered	T3,T4,T17
StIdle	0	0	0	1	-	-	-	Covered	T3,T33,T59
StIdle	0	0	0	0	-	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	1	-	-	Covered	T3,T4,T19
StCtrlRead	-	-	-	-	0	-	-	Covered	T3,T4,T19
StCtrlProg	-	-	-	-	-	1	-	Covered	T3,T4,T17
StCtrlProg	-	-	-	-	-	0	-	Covered	T3,T4,T17
StCtrl	-	-	-	-	-	-	1	Covered	T3,T33,T59
StCtrl	-	-	-	-	-	-	0	Covered	T3,T33,T59
StDisable	-	-	-	-	-	-	-	Covered	T2,T6,T11
default	-	-	-	-	-	-	-	Covered	T6,T13,T14

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ArbCntMax_A	327083568	1691317	0	0
CtrlPrio_A	327083568	1691317	0	0
HostTransIdleChk_A	327083568	18304988	0	0
NoRemainder_A	876	876	0	0
OneHotReqs_A	327083568	326368725	0	0
Pow2Multiple_A	876	876	0	0
RdTxnCheck_A	326968162	326253319	0	0
u_state_regs_A	327083568	326368725	0	0

ArbCntMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	1691317	0	0
T4	317018	9586	0	0
T5	175018	0	0	0
T7	0	550	0	0
T8	0	42642	0	0
T11	4051	0	0	0
T15	4471	0	0	0
T16	996	0	0	0
T17	45527	0	0	0
T18	1042	0	0	0
T19	4161	0	0	0
T20	0	10558	0	0
T21	0	693	0	0
T35	0	1479	0	0
T40	342362	0	0	0
T46	1505	0	0	0
T71	0	23793	0	0
T72	0	47998	0	0
T162	0	2088	0	0
T163	0	1215	0	0

CtrlPrio_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	1691317	0	0
T4	317018	9586	0	0
T5	175018	0	0	0
T7	0	550	0	0
T8	0	42642	0	0
T11	4051	0	0	0
T15	4471	0	0	0
T16	996	0	0	0
T17	45527	0	0	0
T18	1042	0	0	0
T19	4161	0	0	0
T20	0	10558	0	0
T21	0	693	0	0
T35	0	1479	0	0
T40	342362	0	0	0
T46	1505	0	0	0
T71	0	23793	0	0
T72	0	47998	0	0
T162	0	2088	0	0
T163	0	1215	0	0

HostTransIdleChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	18304988	0	0
T4	317018	102360	0	0
T5	175018	0	0	0
T6	131369	65	0	0
T7	0	17440	0	0
T8	0	422995	0	0
T11	4051	0	0	0
T15	4471	0	0	0
T16	996	0	0	0
T17	45527	0	0	0
T18	0	2	0	0
T19	4161	24	0	0
T20	0	91368	0	0
T40	342362	0	0	0
T44	0	29	0	0
T46	1505	0	0	0
T51	0	16	0	0
T71	0	406113	0	0

NoRemainder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

OneHotReqs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	326368725	0	0
T1	9195	9038	0	0
T2	3842	3192	0	0
T3	163740	163662	0	0
T4	317018	316947	0	0
T5	175018	174954	0	0
T6	131369	106175	0	0
T11	4051	3349	0	0
T15	4471	4376	0	0
T16	996	912	0	0
T17	45527	45356	0	0

Pow2Multiple_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

RdTxnCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	326968162	326253319	0	0
T1	9195	9038	0	0
T2	3842	3192	0	0
T3	163740	163662	0	0
T4	317018	316947	0	0
T5	175018	174954	0	0
T6	87997	62803	0	0
T11	4051	3349	0	0
T15	4471	4376	0	0
T16	996	912	0	0
T17	45527	45356	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	326368725	0	0
T1	9195	9038	0	0
T2	3842	3192	0	0
T3	163740	163662	0	0
T4	317018	316947	0	0
T5	175018	174954	0	0
T6	131369	106175	0	0
T11	4051	3349	0	0
T15	4471	4376	0	0
T16	996	912	0	0
T17	45527	45356	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Line No.	Total	Covered	Percent
TOTAL		79	77	97.47
ALWAYS	154	6	6	100.00
ALWAYS	167	3	3	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
ALWAYS	206	4	4	100.00
ALWAYS	218	6	5	83.33
ALWAYS	232	6	5	83.33
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	319	1	1	100.00
CONT_ASSIGN	323	1	1	100.00
ALWAYS	327	29	29	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	578	1	1	100.00
CONT_ASSIGN	585	1	1	100.00
CONT_ASSIGN	602	1	1	100.00
CONT_ASSIGN	603	1	1	100.00
CONT_ASSIGN	604	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
154	1	1
155	1	1
156	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
167	3	3
199	1	1
203	1	1
206	1	1
207	1	1
208	1	1
209	1	1
			MISSING_ELSE
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	0	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	0	1
			MISSING_ELSE
279	1	1
282	1	1
283	1	1
284	1	1
289	1	1
319	1	1
323	1	1
327	1	1
328	1	1
329	1	1
330	1	1
331	1	1
333	1	1
335	1	1
336	1	1
337	1	1
338	1	1
339	1	1
340	1	1
341	1	1
342	1	1
343	1	1
			MISSING_ELSE
349	1	1
350	1	1
351	1	1
			MISSING_ELSE
358	1	1
359	1	1
360	1	1
361	1	1
			MISSING_ELSE
367	1	1
368	1	1
369	1	1
370	1	1
371	1	1
			MISSING_ELSE
376	1	1
377	1	1
390	1	1
394	1	1
395	1	1
396	1	1
397	1	1
398	1	1
399	1	1
400	1	1
417	1	1
430	1	1
550	1	1
578	1	1
585	1	1
602	1	1
603	1	1
604	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Total	Covered	Percent
Conditions	106	97	91.51
Logical	106	97	91.51
Non-Logical	0	0
Event	0	0

 LINE       199
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T7
1	1	Covered	T156,T157

 LINE       199
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       203
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T4
1	1	Not Covered

 LINE       208
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T156,T157

 LINE       220
 EXPRESSION (host_outstanding == '0)
            ------------1-----------

-1-	Status	Tests
0	Covered	T1,T6,T4
1	Covered	T1,T2,T3

 LINE       234
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       234
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T6,T4
1	Covered	T1,T2,T3

 LINE       245
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T4,T7
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T7

 LINE       245
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T7
1	0	1	Covered	T1,T6,T4
1	1	0	Covered	T18,T92,T151
1	1	1	Covered	T1,T4,T7

 LINE       283
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T7,T8
1	1	Covered	T1,T4,T7

 LINE       284
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T4
1	1	Covered	T1,T4,T7

 LINE       319
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T7

 LINE       319
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T158,T159
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T7

 LINE       323
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T7,T8

 LINE       338
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       340
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T17

 LINE       390
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T18,T92,T151
1	0	Covered	T160,T161

 LINE       390
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T160,T161

 LINE       390
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T18,T92,T151

 LINE       390
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       394
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T7

 LINE       395
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T7

 LINE       396
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T7

 LINE       397
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T7

 LINE       398
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       399
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T17

 LINE       400
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

 LINE       400
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T52,T53,T54
1	0	Covered	T1,T2,T3

 LINE       430
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       430
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T4
1	0	Not Covered
1	1	Not Covered

 LINE       430
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T4

 LINE       433
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       433
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T7
1	0	Covered	T1,T2,T3

 LINE       433
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       550
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T17,T40

 LINE       556
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T17,T40

 LINE       556
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T17,T40

 LINE       556
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T17,T40

 LINE       578
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T13,T14
1	0	Covered	T6,T13,T14

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrl	343	Covered	T12
StCtrlProg	341	Covered	T12
StCtrlRead	339	Covered	T12
StDisable	337	Covered	T12
StIdle	351	Covered	T12

transitions	Line No.	Covered	Tests
StCtrl->StIdle	371	Covered	T12
StCtrlProg->StIdle	361	Covered	T12
StCtrlRead->StIdle	351	Covered	T12
StIdle->StCtrl	343	Covered	T12
StIdle->StCtrlProg	341	Covered	T12
StIdle->StCtrlRead	339	Covered	T12
StIdle->StDisable	337	Covered	T12

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Line No.	Total	Covered	Percent
Branches		46	43	93.48
TERNARY	319	2	2	100.00
TERNARY	394	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	396	2	2	100.00
TERNARY	397	2	2	100.00
TERNARY	550	2	2	100.00
TERNARY	433	2	1	50.00
TERNARY	556	2	2	100.00
IF	154	4	4	100.00
IF	167	2	2	100.00
IF	206	3	3	100.00
IF	218	4	3	75.00
IF	232	4	3	75.00
CASE	333	13	13	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	319	((phy_req & host_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	394	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	396	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	397	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	550	(prog_calc_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T17,T40
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	433	(arb_host_gnt_err) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	556	(prog_op_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T17,T40
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	154	if ((!rst_ni))
-2-:	156	if (ctrl_rsp_vld)
-3-:	158	if (inc_arb_cnt)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T4,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	167	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	206	if ((!rst_ni))
-2-:	208	if ((host_gnt_err_event | host_outstanding_err_event))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T156,T157
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	218	if ((!rst_ni))
-2-:	220	if ((host_outstanding == '0))
-3-:	222	if (host_gnt_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Not Covered
0	0	0	Covered	T1,T6,T4

	LineNo.	Expression
-1-:	232	if ((!rst_ni))
-2-:	234	if (((host_outstanding == '0) && ctrl_fsm_idle))
-3-:	236	if (host_outstanding_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	333	case (state_q)
-2-:	336	if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx]))
-3-:	338	if ((ctrl_gnt && rd_i))
-4-:	340	if ((ctrl_gnt && prog_i))
-5-:	342	if (ctrl_gnt)
-6-:	349	if (rd_stage_data_valid)
-7-:	359	if (prog_ack)
-8-:	369	if (erase_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StIdle	1	-	-	-	-	-	-	Covered	T6,T11,T93
StIdle	0	1	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	0	1	-	-	-	-	Covered	T3,T4,T17
StIdle	0	0	0	1	-	-	-	Covered	T1,T2,T3
StIdle	0	0	0	0	-	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	1	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	0	-	-	Covered	T1,T2,T3
StCtrlProg	-	-	-	-	-	1	-	Covered	T3,T4,T17
StCtrlProg	-	-	-	-	-	0	-	Covered	T3,T4,T17
StCtrl	-	-	-	-	-	-	1	Covered	T1,T3,T5
StCtrl	-	-	-	-	-	-	0	Covered	T1,T2,T3
StDisable	-	-	-	-	-	-	-	Covered	T6,T11,T93
default	-	-	-	-	-	-	-	Covered	T6,T13,T14

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ArbCntMax_A	327083568	1882881	0	0
CtrlPrio_A	327083568	1882880	0	0
HostTransIdleChk_A	327083568	18642132	0	0
NoRemainder_A	876	876	0	0
OneHotReqs_A	327083568	326368725	0	0
Pow2Multiple_A	876	876	0	0
RdTxnCheck_A	326968162	326253319	0	0
u_state_regs_A	327083568	326368725	0	0

ArbCntMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	1882881	0	0
T4	317018	5947	0	0
T5	175018	0	0	0
T7	0	2872	0	0
T8	0	46453	0	0
T11	4051	0	0	0
T15	4471	0	0	0
T16	996	0	0	0
T17	45527	0	0	0
T18	1042	0	0	0
T19	4161	0	0	0
T20	0	7563	0	0
T21	0	5868	0	0
T40	342362	0	0	0
T46	1505	0	0	0
T52	0	84	0	0
T71	0	53457	0	0
T72	0	40685	0	0
T162	0	3348	0	0
T163	0	1525	0	0

CtrlPrio_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	1882880	0	0
T4	317018	5947	0	0
T5	175018	0	0	0
T7	0	2872	0	0
T8	0	46453	0	0
T11	4051	0	0	0
T15	4471	0	0	0
T16	996	0	0	0
T17	45527	0	0	0
T18	1042	0	0	0
T19	4161	0	0	0
T20	0	7563	0	0
T21	0	5868	0	0
T40	342362	0	0	0
T46	1505	0	0	0
T52	0	84	0	0
T71	0	53457	0	0
T72	0	40685	0	0
T162	0	3348	0	0
T163	0	1525	0	0

HostTransIdleChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	18642132	0	0
T1	9195	33	0	0
T2	3842	0	0	0
T3	163740	0	0	0
T4	317018	71483	0	0
T5	175018	0	0	0
T6	131369	27	0	0
T7	0	15978	0	0
T8	0	431154	0	0
T11	4051	0	0	0
T15	4471	0	0	0
T16	996	0	0	0
T17	45527	0	0	0
T20	0	83095	0	0
T21	0	29807	0	0
T49	0	16	0	0
T50	0	16	0	0
T71	0	433348	0	0

NoRemainder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

OneHotReqs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	326368725	0	0
T1	9195	9038	0	0
T2	3842	3192	0	0
T3	163740	163662	0	0
T4	317018	316947	0	0
T5	175018	174954	0	0
T6	131369	106175	0	0
T11	4051	3349	0	0
T15	4471	4376	0	0
T16	996	912	0	0
T17	45527	45356	0	0

Pow2Multiple_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

RdTxnCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	326968162	326253319	0	0
T1	9195	9038	0	0
T2	3842	3192	0	0
T3	163740	163662	0	0
T4	317018	316947	0	0
T5	175018	174954	0	0
T6	87997	62803	0	0
T11	4051	3349	0	0
T15	4471	4376	0	0
T16	996	912	0	0
T17	45527	45356	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	327083568	326368725	0	0
T1	9195	9038	0	0
T2	3842	3192	0	0
T3	163740	163662	0	0
T4	317018	316947	0	0
T5	175018	174954	0	0
T6	131369	106175	0	0
T11	4051	3349	0	0
T15	4471	4376	0	0
T16	996	912	0	0
T17	45527	45356	0	0