Toggle Coverage for Module :
prim_secded_inv_64_57_dec
| Total | Covered | Percent |
Totals |
4 |
4 |
100.00 |
Total Bits |
232 |
232 |
100.00 |
Total Bits 0->1 |
116 |
116 |
100.00 |
Total Bits 1->0 |
116 |
116 |
100.00 |
| | | |
Ports |
4 |
4 |
100.00 |
Port Bits |
232 |
232 |
100.00 |
Port Bits 0->1 |
116 |
116 |
100.00 |
Port Bits 1->0 |
116 |
116 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[42:0] |
Yes |
Yes |
*T12,*T22,*T23 |
Yes |
T12,T23,T63 |
INPUT |
data_i[56:43] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
data_i[63:57] |
Yes |
Yes |
T12,T22,T23 |
Yes |
T12,T22,T23 |
INPUT |
data_o[56:0] |
Yes |
Yes |
T12,T22,T23 |
Yes |
T12,T23,T63 |
OUTPUT |
syndrome_o[6:0] |
Yes |
Yes |
T12,T63,T64 |
Yes |
T12,T63,T64 |
OUTPUT |
err_o[1:0] |
Yes |
Yes |
T12,T63,T64 |
Yes |
T12,T63,T64 |
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_reg_core.u_chk.u_chk
| Total | Covered | Percent |
Totals |
4 |
4 |
100.00 |
Total Bits |
232 |
232 |
100.00 |
Total Bits 0->1 |
116 |
116 |
100.00 |
Total Bits 1->0 |
116 |
116 |
100.00 |
| | | |
Ports |
4 |
4 |
100.00 |
Port Bits |
232 |
232 |
100.00 |
Port Bits 0->1 |
116 |
116 |
100.00 |
Port Bits 1->0 |
116 |
116 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[42:0] |
Yes |
Yes |
*T12,*T22,*T23 |
Yes |
T12,T23,T63 |
INPUT |
data_i[56:43] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
data_i[63:57] |
Yes |
Yes |
T12,T22,T23 |
Yes |
T12,T22,T23 |
INPUT |
data_o[56:0] |
Yes |
Yes |
T12,T22,T23 |
Yes |
T12,T23,T63 |
OUTPUT |
syndrome_o[6:0] |
Yes |
Yes |
T12,T64,T60 |
Yes |
T12,T64,T60 |
OUTPUT |
err_o[1:0] |
Yes |
Yes |
T12,T64,T60 |
Yes |
T12,T64,T60 |
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_tl_adapter_eflash.gen_cmd_intg_check.u_cmd_intg_chk.u_chk
| Total | Covered | Percent |
Totals |
4 |
4 |
100.00 |
Total Bits |
232 |
232 |
100.00 |
Total Bits 0->1 |
116 |
116 |
100.00 |
Total Bits 1->0 |
116 |
116 |
100.00 |
| | | |
Ports |
4 |
4 |
100.00 |
Port Bits |
232 |
232 |
100.00 |
Port Bits 0->1 |
116 |
116 |
100.00 |
Port Bits 1->0 |
116 |
116 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[42:0] |
Yes |
Yes |
T63,*T60,T67 |
Yes |
T63,T60,T67 |
INPUT |
data_i[56:43] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
data_i[63:57] |
Yes |
Yes |
T63,T60,T67 |
Yes |
T63,T60,T67 |
INPUT |
data_o[56:0] |
Yes |
Yes |
T63,T60,T67 |
Yes |
T63,T60,T67 |
OUTPUT |
syndrome_o[6:0] |
Yes |
Yes |
T60,T144,T233 |
Yes |
T60,T144,T231 |
OUTPUT |
err_o[1:0] |
Yes |
Yes |
T63,T60,T67 |
Yes |
T60,T61,T144 |
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_chk.u_chk
| Total | Covered | Percent |
Totals |
4 |
4 |
100.00 |
Total Bits |
232 |
232 |
100.00 |
Total Bits 0->1 |
116 |
116 |
100.00 |
Total Bits 1->0 |
116 |
116 |
100.00 |
| | | |
Ports |
4 |
4 |
100.00 |
Port Bits |
232 |
232 |
100.00 |
Port Bits 0->1 |
116 |
116 |
100.00 |
Port Bits 1->0 |
116 |
116 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[42:0] |
Yes |
Yes |
*T12,T63,T60 |
Yes |
T12,T63,T60 |
INPUT |
data_i[56:43] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
data_i[63:57] |
Yes |
Yes |
T12,T63,T60 |
Yes |
T12,T63,T60 |
INPUT |
data_o[56:0] |
Yes |
Yes |
T12,T63,T60 |
Yes |
T12,T63,T60 |
OUTPUT |
syndrome_o[6:0] |
Yes |
Yes |
T63,T60,T144 |
Yes |
T63,T60,T144 |
OUTPUT |
err_o[1:0] |
Yes |
Yes |
T63,T60,T144 |
Yes |
T63,T60,T144 |
OUTPUT |
*Tests covering at least one bit in the range