Module Definition
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Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble.gen_prince.u_cipher

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.40 100.00 86.21 100.00 u_scramble


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble.gen_prince.u_cipher

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.40 100.00 86.21 100.00 u_scramble


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_prince
TotalCoveredPercent
Totals 8 8 100.00
Total Bits 522 522 100.00
Total Bits 0->1 261 261 100.00
Total Bits 1->0 261 261 100.00

Ports 8 8 100.00
Port Bits 522 522 100.00
Port Bits 0->1 261 261 100.00
Port Bits 1->0 261 261 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T6 Yes T1,T2,T3 INPUT
valid_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_i[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
key_i[127:0] Yes Yes T1,T2,T11 Yes T1,T2,T11 INPUT
dec_i Yes Yes T4,T17,T19 Yes T4,T17,T19 INPUT
valid_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT

Toggle Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble.gen_prince.u_cipher
TotalCoveredPercent
Totals 8 8 100.00
Total Bits 522 522 100.00
Total Bits 0->1 261 261 100.00
Total Bits 1->0 261 261 100.00

Ports 8 8 100.00
Port Bits 522 522 100.00
Port Bits 0->1 261 261 100.00
Port Bits 1->0 261 261 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T6 Yes T1,T2,T3 INPUT
valid_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_i[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
key_i[127:0] Yes Yes T1,T2,T11 Yes T1,T2,T11 INPUT
dec_i Yes Yes T4,T17,T40 Yes T4,T17,T40 INPUT
valid_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
data_o[63:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT

Toggle Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble.gen_prince.u_cipher
TotalCoveredPercent
Totals 8 8 100.00
Total Bits 522 522 100.00
Total Bits 0->1 261 261 100.00
Total Bits 1->0 261 261 100.00

Ports 8 8 100.00
Port Bits 522 522 100.00
Port Bits 0->1 261 261 100.00
Port Bits 1->0 261 261 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T6 Yes T1,T2,T3 INPUT
valid_i Yes Yes T4,T19,T7 Yes T4,T19,T7 INPUT
data_i[63:0] Yes Yes T3,T4,T19 Yes T3,T4,T19 INPUT
key_i[127:0] Yes Yes T1,T2,T11 Yes T1,T2,T11 INPUT
dec_i Yes Yes T4,T19,T44 Yes T4,T19,T44 INPUT
valid_o Yes Yes T4,T19,T7 Yes T4,T19,T7 OUTPUT
data_o[63:0] Yes Yes T1,T4,T15 Yes T1,T4,T11 OUTPUT

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